-
1
-
-
0022313711
-
"Low-voltage operational amplifier with rail-to-rail input and output ranges"
-
Dec
-
J. Huijsing and D. Linebarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1144-1150, Dec. 1985.
-
(1985)
IEEE J. Solid-State Circuits
, vol.SC-20
, Issue.6
, pp. 1144-1150
-
-
Huijsing, J.1
Linebarger, D.2
-
2
-
-
0025414531
-
"A rail-to-rail input/output CMOS power amplifier"
-
M. Pardoen and M. Degrauwe, "A rail-to-rail input/output CMOS power amplifier," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 501-504, Apr. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.2
, pp. 501-504
-
-
Pardoen, M.1
Degrauwe, M.2
-
3
-
-
0025384745
-
"A CMOS large-swing low-distortion three-stage class AB power amplifier"
-
Feb
-
F. Op'T EEynde, P. Ampe, L. Verdeyen, and W. Sansen, "A CMOS large-swing low-distortion three-stage class AB power amplifier," IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 265-273, Feb. 1990.
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.1
, pp. 265-273
-
-
Op'T Eeynde, F.1
Ampe, P.2
Verdeyen, L.3
Sansen, W.4
-
4
-
-
0026366569
-
"Operational amplifier with 1-V rail-to-rail multipath-driven output stage"
-
Dec
-
J. Fonderie and J. Huijsing, "Operational amplifier with 1-V rail-to-rail multipath-driven output stage," IEEE J. Solid-State Circuits, vol. 26, no. 12, pp. 1817-1824, Dec. 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, Issue.12
, pp. 1817-1824
-
-
Fonderie, J.1
Huijsing, J.2
-
5
-
-
0028754530
-
"A Programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested miller compensation for 120 dB gain and 6 MHz UGF"
-
Dec
-
R. Eschauzier, R. Hogervorst, and J. Huijsing, "A Programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested miller compensation for 120 dB gain and 6 MHz UGF," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1497-1504, Dec. 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, Issue.12
, pp. 1497-1504
-
-
Eschauzier, R.1
Hogervorst, R.2
Huijsing, J.3
-
6
-
-
0033097422
-
"A multistage amplifier technique with embedded frequency compensation"
-
Mar
-
H. Ng, R. Ziazadeh, and D. Allstot, "A multistage amplifier technique with embedded frequency compensation," IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 339-347, Mar. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.3
, pp. 339-347
-
-
Ng, H.1
Ziazadeh, R.2
Allstot, D.3
-
8
-
-
0031356398
-
"Multistage amplifier topologies with nested Gm-C compensation"
-
Dec
-
F. You, S. Embabi, and E. Sanchez-Sinencio, "Multistage amplifier topologies with nested Gm-C compensation," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2000-2011, Dec. 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, Issue.12
, pp. 2000-2011
-
-
You, F.1
Embabi, S.2
Sanchez-Sinencio, E.3
-
9
-
-
0033907216
-
"Three-stage large capacitive load amplifier with dumping-factor-control frequency compensation"
-
Feb
-
K. Leung, P. Mok, W. Ki, and J. Sin, "Three-stage large capacitive load amplifier with dumping-factor-control frequency compensation," IEEE J. Solid-State Circuits, vol. SC-35, no. 2, pp. 221-230, Feb. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.SC-35
, Issue.2
, pp. 221-230
-
-
Leung, K.1
Mok, P.2
Ki, W.3
Sin, J.4
-
10
-
-
0036647564
-
"Design methodology and advances in nested-Miller compensation"
-
Jul
-
G. Palumbo and S. Pennisi, "Design methodology and advances in nested-Miller compensation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 7, pp. 893-903, Jul. 2002.
-
(2002)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
, vol.49
, Issue.7
, pp. 893-903
-
-
Palumbo, G.1
Pennisi, S.2
-
11
-
-
0037608791
-
"Design guidelines for reversed nested Miller compensation"
-
May
-
R. Mita, G. Palumbo, and S. Pennisi, "Design guidelines for reversed nested Miller compensation," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 50, no. 5, pp. 227-233, May 2003.
-
(2003)
IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process.
, vol.50
, Issue.5
, pp. 227-233
-
-
Mita, R.1
Palumbo, G.2
Pennisi, S.3
-
12
-
-
0015205886
-
"The output properties of volterra systems (nonlinear systems with memory) driven by harmonic and gaussian inputs"
-
Dec
-
E. Bedrosian and S. Rice, "The output properties of volterra systems (nonlinear systems with memory) driven by harmonic and gaussian inputs," Proc. IEEE, vol. 59, no. 12, pp. 1688-1707, Dec. 1971.
-
(1971)
Proc. IEEE
, vol.59
, Issue.12
, pp. 1688-1707
-
-
Bedrosian, E.1
Rice, S.2
-
13
-
-
0015300757
-
"Cross modulation and intermodulation in amplifiers at high frequency"
-
Feb
-
R. Meyer, M. Shensa, and R. Eschenbach, "Cross modulation and intermodulation in amplifiers at high frequency," IEEE J. Solid-State Circuits, vol. SC-7, no. 1, pp. 16-23, Feb. 1972.
-
(1972)
IEEE J. Solid-State Circuits
, vol.SC-7
, Issue.1
, pp. 16-23
-
-
Meyer, R.1
Shensa, M.2
Eschenbach, R.3
-
14
-
-
0015640432
-
"An analysis of distortion in bipolar transistors using integral charge control model and volterra series"
-
Jul
-
S. Narayanan and C. Poon, "An analysis of distortion in bipolar transistors using integral charge control model and volterra series," IEEE Trans. Circuit Theory, vol. CT-20, no. 4, pp. 341-351, Jul. 1973.
-
(1973)
IEEE Trans. Circuit Theory
, vol.CT-20
, Issue.4
, pp. 341-351
-
-
Narayanan, S.1
Poon, C.2
-
15
-
-
0032659047
-
"High-frequency distortion analysis of analog integrated circuits"
-
Mar
-
P. Wambacq, G. Gielen, P. Kinget, and W. Sansen, "High-frequency distortion analysis of analog integrated circuits," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 46, no. 3, pp. 335-344, Mar. 1999.
-
(1999)
IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process.
, vol.46
, Issue.3
, pp. 335-344
-
-
Wambacq, P.1
Gielen, G.2
Kinget, P.3
Sansen, W.4
-
16
-
-
0032639862
-
"Distortion in elementary transistor circuits"
-
Mar
-
W. Sansen, "Distortion in elementary transistor circuits," IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process., vol. 46, no. 3, pp. 315-324, Mar. 1999.
-
(1999)
IEEE Trans. Circuits Syst. II, Analog. Digit. Signal Process.
, vol.46
, Issue.3
, pp. 315-324
-
-
Sansen, W.1
-
19
-
-
20144381807
-
"Distortion in single-, two- and three-stage amplifiers"
-
May
-
B. Hernes and W. Sansen, "Distortion in single-, two- and three-stage amplifiers," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 52, no. 5, pp. 846-856, May 2005.
-
(2005)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
, vol.52
, Issue.5
, pp. 846-856
-
-
Hernes, B.1
Sansen, W.2
-
22
-
-
0032074915
-
"Harmonic distortion in nonlinear amplifier with nonlinear feedback"
-
G. Palumbo and S. Pennisi, "Harmonic distortion in nonlinear amplifier with nonlinear feedback," J. Circuit Theory Appl., vol. 26, pp. 293-299, 1998.
-
(1998)
J. Circuit Theory Appl.
, vol.26
, pp. 293-299
-
-
Palumbo, G.1
Pennisi, S.2
-
23
-
-
0038681916
-
"High-frequency harmonic distortion in feedback amplifiers: Analysis and applications"
-
Mar
-
G. Palumbo and S. Pennisi, "High-frequency harmonic distortion in feedback amplifiers: Analysis and applications," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 3, pp. 328-340, Mar. 2003.
-
(2003)
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
, vol.50
, Issue.3
, pp. 328-340
-
-
Palumbo, G.1
Pennisi, S.2
-
24
-
-
4344669439
-
"Harmonic distortion in three-stage nested-Miller-compensated amplifiers"
-
Vancouver, BC, Canada, May
-
G. Palumbo and S. Pennisi, "Harmonic distortion in three-stage nested-Miller-compensated amplifiers," in Proc. IEEE ISCAS'04, vol. I, Vancouver, BC, Canada, May 2004, pp. 485-488.
-
(2004)
Proc. IEEE ISCAS'04
, vol.1
, pp. 485-488
-
-
Palumbo, G.1
Pennisi, S.2
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