Role of nitrogen on the gate length dependence of NBTI

IEEE Electron Device Letters

Volumn 30, Issue 7, 2009, Pages 772-774

  Ho, T J J ^a   Ang, D S ^a   Tang, L ^b   Phua, T W H ^c   Ng, C M ^c  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

Bias temperature instability (BTI); Decoupled plasma nitridation; Device reliability; MOSFET scaling; Oxynitride; Thermal nitridation

Indexed keywords

BIAS-TEMPERATURE INSTABILITY (BTI); DECOUPLED PLASMA NITRIDATION; DEVICE RELIABILITY; MOSFET SCALING; OXYNITRIDE; THERMAL NITRIDATION;

ELECTRON ENERGY LOSS SPECTROSCOPY; ENERGY DISSIPATION; GATE DIELECTRICS; GATES (TRANSISTOR); MOS DEVICES; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; NITRIDATION; NITRIDES; NITROGEN; PLASMA DIAGNOSTICS; PLASMAS; SILICON COMPOUNDS; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

PLASMA STABILITY;

EID: 67650438361     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2022348     Document Type: Article

References (13)

1. N. Kimizuka, K. Yamaguchi, K. Imai, T. Iizuka, C. T. Liu, R. C. Keller, and T. Horiuchi, "NBTI enhancement by nitrogen incorporation into ultrathin gate oxide for 0.10-μm gate CMOS generation," in VLSI Symp. Tech. Dig., 2000, pp. 92-93.
2. Y. Mitani, M. Nagamine, H. Satake, and A. Toriumi, "NBTI mechanism in ultra-thin gate dielectric - Nitrogen-originated mechanism in SiON," in IEDM Tech. Dig., 2002, pp. 509-512.
3. D. S. Ang and K. L. Pey, "Evidence for two distinct positive trapped charge components in NBTI stressed p-MOSFETs employing ultrathin CVD silicon nitride gate dielectrics," IEEE Electron Device Lett., vol. 25, no. 9, pp. 637-639, Sep. 2004.
4. D. S. Ang, S. Wang, and C. H. Ling, "Evidence of two distinct degradation mechanisms from temperature dependence of negative bias stressing of the ultrathin gate p-MOSFET," IEEE Electron Device Lett., vol. 26, no. 12, pp. 906-908, Dec. 2005.
5. D. S. Ang and S. Wang, "On the non-Arrhenius behavior of negative-bias temperature instability," Appl. Phys. Lett., vol. 88, no. 9, art no. 903 506, Feb. 2006.
6. D. S. Ang and S. Wang, "Insight into the suppressed recovery of NBTI-stressed ultrathin oxynitride gate pMOSFET," IEEE Electron Device Lett., vol. 27, no. 9, pp. 755-758, Sep. 2006.
7. D. S. Ang, S. Wang, G. A. Du, and Y. Z. Hu, "A consistent deep-level hole trapping model for negative bias temperature instability," IEEE Trans. Device Mater. Rel., vol. 8, no. 1, pp. 22-34, Mar. 2008.
8. + polysilicon gate p-MOSFETs," IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 921-926, May 1999.
9. 2-GD) method," in IEDM Tech. Dig., 2002, pp. 513-516.
10. D. C. Sekhar, P. P. Ray, M. M. De Souza, and P. Chaparala, "Edge effect under temperature bias stress of 0.18 μm PMOS technology," in Proc. Int. Conf. Microelectron., 2004, pp. 645-648.
11. G. Cellere, M. G. Valentini, and A. Paccagnella, "Effect of channel width, length, and latent damage on NBTI," in Proc. Int. Conf. IC Des. Technol., 2004, pp. 303-306.
12. T. J. J. Ho, D. S. Ang, Z. Q. Teo, and C. M. Ng, "Channel length dependence of NBTI: Increased generation of deep-level hole traps at the source/drain extension regions," in Proc. Semicond. Interface Spec. Conf., 2008, pp. P21.1-P21.2.
13. A. E. Islam, V. D. Maheta, H. Das, S. Mahapatra, and M. A. Alam, "Mobility degradation due to interface traps in plasma oxynitride PMOS devices," in Proc. Int. Reliab. Phys. Symp., 2008, pp. 87-96.