Edge effect under temperature bias stress of 0.18μm PMOS technology

Proceedings of the International Conference on Microelectronics

Volumn 24 II, Issue , 2004, Pages 645-648

  Sekhar, D Chandra ^a   Ray, Partha Pratim ^a   De Souza, M M ^a   Chaparala, Prasad ^b  

^a DE MONTFORT UNIVERSITY   (United Kingdom)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

PMOSFET; Series resistance (RSD); Temperature measurement

Indexed keywords

CAPACITANCE; DEGRADATION; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; EXTRAPOLATION; INTERFACES (MATERIALS); SILICA; STRESS ANALYSIS; TEMPERATURE MEASUREMENT;

BIAS STRESS; EDGE EFFECTS; PMOSFET; SERIES RESISTANCE (RSD);

MOSFET DEVICES;

EID: 3142715230     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. D. K. Schroder and J. A. Babcock "Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing", J. Appl. Phys., 2003, vol. 94, pp. 1-18.
2. P. Chaparala, J. Shibley and P. Lim, "Threshold voltage drift in PMOSFETs due to NBTI and HCI", IEEE Integrated Reliability Workshop, 2000, pp. 95-97.
3. M. Houssa, C. Parthasarathy, N. Espreux, N. Revil and J. L. Autran "Model for negative bias temperature instability in p-MOSFETs with ultrathin oxynitride layers" J. Non-crystalline Solids, 2003, vol. 322, pp. 100-104.
4. Y. H. Lee, K. Wu, T. Linton, N. Mielke, S. Hu and B. Wallace, "Channel-width dependent hot-carrier degradation of thin-gate pMOSFETs" IEEE Intl. Rel. Phys. Symp. Proc., 2000, pp. 77-82.
5. K. O. Jeppson and C. M. Svensson, "Negative Bias stress of MOS devices at high electric fields and degradation of NMOS devices," J. Appl. Phys., 1977, vol. 48, pp. 2004-2014.
6. V. Huard, F. Monsieur, G. Ribes, S. Bruyere, "Evidence for hydrogen-related defects during NBTI stress in p-MOSFETs", IEEE Intl. Rel. Phys. Symp. Proc., 2003, pp. 178-182
7. J.F.Zhang and W. Eccleston, "Positive bias temperature instability in MOSFET's", IEEE Trans. Elec. Dev., 1998, vol.45, pp. 116-124.
8. T. Yamamoto, K. Uwasawa, and T. Mogami, "Bias temperature instability in scaled P+ poly silicon gate p-MOSFET's" IEEE Trans. Elec. Dev., 1999, vol.46, pp. 921-926.
9. P. J. McWhorter and P. S. Winokur, "Simple technique for separating the effects of interface traps and trapped oxide charge in metal-oxide- semiconductor transistors" Appl. Phys. Lett., 1986, vol. 48, pp.133-135.
10. nd ed. (Wilely, New York, 1981), p.446
11. F. H. de La Moneda, H. N. Kotecha and M. Shatzkes, "Measurement of MOSFET constants", IEEE Elec. Dev. Lett., 1982, vol. 3, pp. 10-12.
12. M. M. De Souza, S. K. Manhas, D. Chandra Sekhar, A. S. Oates and P. Chaparala, "Influence of mobility model on extraction of stress dependent source-drain series resistance", Microlectronics Reliability, 2004, vol. 44, pp. 25-32.
13. T. Hori "Gate dielectrics and MOS ULSIs" Springer series in electrophysics, 1997, p. 129.