Simulation of nanofloating gate memory with high-k stacked dielectrics

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn 2003-January, Issue , 2003, Pages 299-302

  Govoreanu, B ^a,b   Blomme, P ^a,b   Van Houdt, J ^a   De Meyer, K ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Character generation; CMOS technology; Dielectric constant; Dielectric substrates; Doping; High K dielectric materials; High K gate dielectrics; Nonvolatile memory; Threshold voltage; Tunneling

Indexed keywords

CMOS INTEGRATED CIRCUITS; DOPING (ADDITIVES); ELECTRON TUNNELING; GATE DIELECTRICS; NONVOLATILE STORAGE; PERMITTIVITY; SEMICONDUCTOR DEVICES; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

CHARACTER GENERATION; CMOS TECHNOLOGY; DIELECTRIC SUBSTRATES; HIGH- K GATE DIELECTRICS; HIGH-K DIELECTRIC MATERIALS; NON-VOLATILE MEMORY;

DIELECTRIC MATERIALS;

EID: 67650209701     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2003.1233696     Document Type: Conference Paper

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