A 20-Gb/s coaxial cable receiver analog front-end in 90-nm CMOS technology

Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Volumn , Issue , 2008, Pages 225-228

  Park, Peter ^a   Carusone, Anthony Chan ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

20 GB/S; ANALOG FRONT-END; CABLE CHANNEL; CMOS PROCESS; CMOS TECHNOLOGY; DATA STREAM; DC-BIAS CURRENT; FEEDBACK RESISTORS; INPUT SENSITIVITY; LEVEL-SHIFTING; SHUNT-SHUNT FEEDBACK;

CMOS INTEGRATED CIRCUITS; COAXIAL CABLES; ELECTRIC CABLES; TELECOMMUNICATION CABLES;

AMPLIFIERS (ELECTRONIC);

EID: 67649964645     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2008.4708769     Document Type: Conference Paper

References (12)

1. S. Shahramian, S. P. Voinigescu, and A. C. Carusone, "A 30-GS/sec track and hold amplifier in 0.13-μm CMOS technology," Proc. IEEE CICC, pp. 493-496, September 2006.
2. T. O. Dickson, K. H. Yau, T. Chalvatzis, A. M. Mangan, E. Laskin, R. Beerkens, P. Westergaard, M. Tazlauanu, M.-T. Yang, and S. P. Voinigescu, "The invariance of characteristic current densities in nanoscale mosfets and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks," IEEE J. Solid-State Circuits, vol. 41, no. 8, August 2006.
3. T. H. Lee, Planar microwave engineering : a practical guide to theory, measurement, and circuits. Cambridge University Press, 2004.
4. H. Tran, F. Pera, D. S. McPherson, D. Viorel, and S. P. Voinigescu, "6-kω 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range," IEEE J. Solid-State Circuits, vol. 39, no. 10, October 2004.
5. M. Hossain and A. C. Carusone, "A 19-GHz broadband amplifier using a gm-boosted cascode in 0.18-μm CMOS," Proc. IEEE CICC, pp. 829-832, September 2006.
6. G. E. Zhang and M. M. Green, "A 10 Gb/s BiCMOS adaptive cable equalizer," IEEE J. Solid-State Circuits, vol. 40, no. 11, November 2005.
7. C.-F. Liao and S.-I. Liu, "A 40Gb/s CMOS serial-link receiver with adaptive equalization and CDR," Proc. IEEE International Solid-State Circuits Conference, February 2008.
8. J. A. Dobrowolski, Introduction to Computer Methods for Microwave Circuit Analysis and Design. Artech House, Inc., 1991.
9. S. Gondi, J. Lee, D. Takeuchi, and B. Razavi, "A 10Gb/s CMOS adaptive equalizer for backplane applications," Proc. IEEE International Solid-State Circuits Conference, February 2005.
10. J. Lee, "A 20-Gb/s adaptive equalizer in 0.13-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 41, no. 9, September 2006.
11. Y. Tomita, M. Kibune, J. Ogawa, W. W. Walker, H. Tamura, and T. Kuroda, "A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS," IEEE J. Solid-State Circuits, vol. 40, no. 4, April 2005.
12. J. Sewter and A. C. Carusone, "A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s," IEEE J. Solid-State Circuits, vol. 41, no. 4, April 2006.