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A 1-tap 40-Gbps look-ahead decision feedback equalizer in 0.18μm SiGe BiCMOS technology
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49-Gb/s, 7-tap transversal filter in 0.18μm SiGe BiCMOS for backplane equalization
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Oct
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A. Hazneci and S. P. Voinigescu, "49-Gb/s, 7-tap transversal filter in 0.18μm SiGe BiCMOS for backplane equalization," in CSICS, Proceedings of the IEEE, Oct. 2004, pp. 101-104.
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Hazneci, A.1
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A 22GS/s 5b ADC in 0.13μm SiGe BiCMOS
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Feb
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P. Schvan, D. Pollex, S. Wang, C. Falt, and N. B. Hamida, "A 22GS/s 5b ADC in 0.13μm SiGe BiCMOS," in Solid-State Circuits Conference, IEEE International, Digest of Technical Papers, Feb. 2006, pp. 572-573.
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Schvan, P.1
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Fully Bipolar, 120-MSample/s 10-b track-and-hold circuit
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30944451800
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A 40-GSamples/Sec Track & Hold Amplifier in 0.18μm SiGe BiCMOS technology
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Oct
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S. Shahramian, A. C. Carusone, and S. Voinigescu, "A 40-GSamples/Sec Track & Hold Amplifier in 0.18μm SiGe BiCMOS technology," in CSICS, Proceedings of the IEEE, Oct. 2005, pp. 101-104.
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Shahramian, S.1
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17644364795
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4-Gb/s Track and Hold Circuit using Parasitic Capacitance Canceller
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Sept
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T. Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, and H. Okada, "4-Gb/s Track and Hold Circuit using Parasitic Capacitance Canceller," in ESSCIRC, Proceeding of the IEEE, Sept. 2004, pp. 347-350.
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A 10-b 185-MS/s Track-and-Hold in 0.35-μm CMOS
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Feb
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A. Boni, A. Pierazzi, and C. Morandi, "A 10-b 185-MS/s Track-and-Hold in 0.35-μm CMOS," IEEE J. Solid-State Circuits, pp. 195-203, Feb. 2001.
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Boni, A.1
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Differentially pre-compensated GHz-range low-voltage track-and-hold
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Jan
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N. Tchamov, M. Velichkov, A. Keranen, and V. Stoyanov, "Differentially pre-compensated GHz-range low-voltage track-and-hold," in Electronic Letters, Jan. 2003, p. 180.
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An 8-bit, 12 GSample/sec SiGe track-and-hold amplifier
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Oct
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Y. Lu, W. Kuo, X. Li, R. Krithivasan, J. Cressler, Y. Borokhovych, H. Gustat, B. Tillack, and B. Heinemann, "An 8-bit, 12 GSample/sec SiGe track-and-hold amplifier," in BCTM, Proceedings of the IEEE, Oct. 2005, pp. 148-151.
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10
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0042280611
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6-b 12-GSamples/S track-and-hold amplifier in InP DHBT Technology
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Sept
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J. Lee, A. Leven, J. Weiner, Y. Baeyens, Y. Yang, W Sung, J. Frachoviak, R. Kopf, and Y.-K. Chen, "6-b 12-GSamples/S track-and-hold amplifier in InP DHBT Technology," IEEE J. Solid-State Circuits, pp. 1533-1539, Sept. 2003.
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11
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33749523503
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Algorithmic Design Methodologies and Design Porting of Wireline Transceiver IC Building Blocks Between Technology Nodes
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Sept
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S. Voinigescu, T. Dickson, T. Chalvatzis, A. Hazneci, E. Laskinand, R. Beerkens, and I. Khalid, "Algorithmic Design Methodologies and Design Porting of Wireline Transceiver IC Building Blocks Between Technology Nodes," in CICC, Proceedings of the IEEE, Sept. 2005, pp. 110-117.
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12
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33845879133
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An SOI CMOS, High Gain and Low Noise Transimpedance-Limiting Amplifier for 10Gb/s Applications
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June, to appear
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F. Pera and S. Voinigescu, "An SOI CMOS, High Gain and Low Noise Transimpedance-Limiting Amplifier for 10Gb/s Applications," in RFIC, June 2006, to appear.
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RFIC
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