New subthreshold concepts in 65nm CMOS technology

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 162-166

  Moradi, Farshad ^a   Wisland, Dag T ^a   Mahmoodi, Hamid ^b   Peiravi, Ali ^c   Aunet, Snorre ^a   Cao, Tuan Vu ^a  

^a UNIVERSITY OF OSLO   (Norway)

^b SAN FRANCISCO STATE UNIVERSITY   (United States)

^c FERDOWSI UNIVERSITY OF MASHHAD   (Iran)

Author keywords

Low power; Low voltage; Nanoscale; Subthreshold

Indexed keywords

65NM CMOS TECHNOLOGY; 65NM TECHNOLOGY; HOLD TIME; LOW POWER APPLICATION; LOW SUPPLY VOLTAGES; LOW-POWER; LOW-VOLTAGE; NANOSCALE; POWER CONSUMPTION; SET-UP TIME; SIMULATION RESULT; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; SUBTHRESHOLD REGION;

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; NANOSTRUCTURED MATERIALS; TOPOLOGY;

ELECTRIC NETWORK ANALYSIS;

EID: 67649669583     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810287     Document Type: Conference Paper

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