Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 430-435

  Liu, Bao ^a  

^a The University of Texas at San Antonio   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE VOLTAGE; ADDRESSING METHOD; AGGRESSIVE SCALING; DATA LINE; ELECTRICAL PARAMETER; GATE VOLTAGES; HIGH VOLTAGE; LAYOUT DESIGNS; NANO SCALE; NANO-INTERFACE; NANO-SCALE SYSTEM; NANOELECTRONIC SYSTEMS; NANOSCALE WIRES; PHYSICAL STRUCTURES; RESISTIVE VOLTAGE DIVIDERS; SPICE SIMULATIONS; SUBTHRESHOLD SLOPE; TIME DOMAIN; VOLTAGE-CONTROLLED; YIELD IMPROVEMENT;

DESIGN; NANOSTRUCTURED MATERIALS; NANOWIRES; SPICE; TIME DOMAIN ANALYSIS; VOLTAGE DIVIDERS; WIRE;

NANOELECTRONICS;

EID: 67649640013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810333     Document Type: Conference Paper

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