A systematic approach to modeling and analysis of transient faults in logic circuits

Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Volumn , Issue , 2009, Pages 408-413

  Miskov Zivanov, Natasa ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MODELING AND ANALYSIS; MULTIPLE BIT UPSET; ORDERS OF MAGNITUDE; OUTPUT ERRORS; PHYSICAL PHENOMENA; SOFT ERROR; SOFT ERROR RATE; TECHNOLOGY SCALING; TRANSIENT BEHAVIOR; TRANSIENT FAULTS;

ERROR CORRECTION; MICROPROCESSOR CHIPS; SEQUENTIAL CIRCUITS; SWITCHING CIRCUITS; TRANSIENTS;

ELECTRIC NETWORK ANALYSIS;

EID: 67649635985     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2009.4810329     Document Type: Conference Paper

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