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Volumn 4148 LNCS, Issue , 2006, Pages 169-180

Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CORRELATION METHODS; GRAPHIC METHODS; SIGNAL ENCODING; STATISTICAL METHODS; TELECOMMUNICATION SYSTEMS;

EID: 33750037318     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11847083_17     Document Type: Conference Paper
Times cited : (7)

References (14)
  • 3
    • 84874603501 scopus 로고    scopus 로고
    • International technology roadmap for semiconductors, 2005 Edition
    • Jan.
    • International Technology Roadmap for Semiconductors, 2005 Edition. Interconnect. http://www.itrs.net/, Jan. 2006.
    • (2006) Interconnect
  • 6
    • 0036907052 scopus 로고    scopus 로고
    • Coupling-aware high-level interconnect synthesis for low power
    • San Jose, California, Nov.
    • C.-G. Lyuh, T. Kim, and K.-W. Kim. Coupling-Aware High-level Interconnect Synthesis for Low Power. In Intl. Conf. on Computer-Aided Design (ICCAD), pages 609-613, San Jose, California, Nov. 2002.
    • (2002) Intl. Conf. on Computer-aided Design (ICCAD) , pp. 609-613
    • Lyuh, C.-G.1    Kim, T.2    Kim, K.-W.3
  • 11
    • 0033725613 scopus 로고    scopus 로고
    • Low power coding techniques considering inter-wire capacitance
    • Orlando, Florida, May
    • P. P. Sotiriadis and A. P. Chandrakasan. Low Power Coding Techniques Considering Inter-Wire Capacitance. In Custom Integrated Circuits Conf., pages 507-510, Orlando, Florida, May 2000.
    • (2000) Custom Integrated Circuits Conf. , pp. 507-510
    • Sotiriadis, P.P.1    Chandrakasan, A.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.