Ultra-low power subthreshold current-mode logic utilising PMOS load device

Electronics Letters

Volumn 43, Issue 17, 2007, Pages 911-913

  Tajalli, A ^a   Vittoz, E ^a   Leblebici, Y ^a   Brauer, E J ^b  

^a EPFL   (Switzerland)

^b Northern Arizona University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS CURRENTS; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; NATURAL FREQUENCIES;

PMOS LOAD DEVICE; WITH ULTRA-LOW BIAS CURRENTS;

MOS DEVICES;

EID: 34548027940     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20071208     Document Type: Article

References (5)

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3. Soeleman, H., Roy, K., and Paul, B.C.: ' Robust subthreshold logic for ultra-low power operation ', IEEE Trans. Very-Large Scale Integr. (VLSI) Syst., 2001, 9, (1), p. 90-99
4. Cannillo, F., and Toumazou, C.: ' Nano-power subthreshold current-mode logic in sub-100nm technologies ', Electron. Lett., 2005, 41, (23), p. 1268-1269 0013-5194
5. Enz, C.C., Krummenacher, F., and Vittoz, E.A.: ' An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current appliations ', Analog Integr. Circuits Signal Process., 1995, 5, p. 83-114 0925-1030