-
1
-
-
33847734692
-
BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability
-
H. T. Lue, S. Y. Wang, E. K. Lai, Y. H. Shih, S. C. Lai, L. W. Yang, K. C. Chen, J. Ku, K. Y. Hsieh, R. Liu, and C. Y. Lu, "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," in IEDM Tech. Dig., 2005, pp. 547-550.
-
(2005)
IEDM Tech. Dig
, pp. 547-550
-
-
Lue, H.T.1
Wang, S.Y.2
Lai, E.K.3
Shih, Y.H.4
Lai, S.C.5
Yang, L.W.6
Chen, K.C.7
Ku, J.8
Hsieh, K.Y.9
Liu, R.10
Lu, C.Y.11
-
2
-
-
33847749484
-
A novel NAND-type MONOS memory using 63 nm process technology for multi-gigabit flash EEPROMs
-
Y. Shin, J. Choi, C. Kang, C. Lee, K. T. Park, J. S. Lee, J. Sel, V. Kim, B. Choi, J. Sim, D. Kim, H. J. Cho, and K. Kim, "A novel NAND-type MONOS memory using 63 nm process technology for multi-gigabit flash EEPROMs," in IEDM Tech. Dig., 2005, pp. 337-340.
-
(2005)
IEDM Tech. Dig
, pp. 337-340
-
-
Shin, Y.1
Choi, J.2
Kang, C.3
Lee, C.4
Park, K.T.5
Lee, J.S.6
Sel, J.7
Kim, V.8
Choi, B.9
Sim, J.10
Kim, D.11
Cho, H.J.12
Kim, K.13
-
3
-
-
21644487861
-
Impact of few electron phenomena on floating-gate memory reliability
-
G. Molas, D. Deleruyelle, B. De Salvo, G. Ghibaudo, M. Gely, S. Jacob, D. Lafond, and S. Deleonibus, "Impact of few electron phenomena on floating-gate memory reliability," in IEDM Tech. Dig., 2004, pp. 877-880.
-
(2004)
IEDM Tech. Dig
, pp. 877-880
-
-
Molas, G.1
Deleruyelle, D.2
De Salvo, B.3
Ghibaudo, G.4
Gely, M.5
Jacob, S.6
Lafond, D.7
Deleonibus, S.8
-
4
-
-
51949115623
-
Scaling evaluation of BE-SONOS NAND flash beyond 20 nm
-
H. T. Lue, T. H. Hsu, S. C. Lai, Y. H. Hsiao, W. C. Peng, C. W. Liao, Y. F. Huang, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C.-Y. Lu, "Scaling evaluation of BE-SONOS NAND flash beyond 20 nm," in VLSI Symp. Technol., 2008, pp. 116-117.
-
(2008)
VLSI Symp. Technol
, pp. 116-117
-
-
Lue, H.T.1
Hsu, T.H.2
Lai, S.C.3
Hsiao, Y.H.4
Peng, W.C.5
Liao, C.W.6
Huang, Y.F.7
Hong, S.P.8
Wu, M.T.9
Hsu, F.H.10
Lien, N.Z.11
Wang, S.Y.12
Yang, L.W.13
Yang, T.14
Chen, K.C.15
Hsieh, K.Y.16
Liu, R.17
Lu, C.-Y.18
-
5
-
-
43549124664
-
A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET
-
T. H. Hsu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, L. W. Yang, Y. C. King, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A high-speed BE-SONOS NAND flash utilizing the field-enhancement effect of FinFET," in IEDM Tech. Dig., 2007, pp. 913-916.
-
(2007)
IEDM Tech. Dig
, pp. 913-916
-
-
Hsu, T.H.1
Lue, H.T.2
Lai, E.K.3
Hsieh, J.Y.4
Wang, S.Y.5
Yang, L.W.6
King, Y.C.7
Yang, T.8
Chen, K.C.9
Hsieh, K.Y.10
Liu, R.11
Lu, C.Y.12
-
6
-
-
50249133173
-
Study of local trapping and STI edge effects on charge-trapping NAND flash
-
H. T. Lue, T. H. Hsu, S. Y. Wang, Y. H. Hsiao, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, and C. Y. Lu, "Study of local trapping and STI edge effects on charge-trapping NAND flash," in IEDM Tech. Dig., 2007, pp. 161-164.
-
(2007)
IEDM Tech. Dig
, pp. 161-164
-
-
Lue, H.T.1
Hsu, T.H.2
Wang, S.Y.3
Hsiao, Y.H.4
Lai, E.K.5
Yang, L.W.6
Yang, T.7
Chen, K.C.8
Hsieh, K.Y.9
Liu, R.10
Lu, C.Y.11
-
7
-
-
4544344826
-
Sub-40 nm tri-gate charge trapping nonvolatile memory cells for high-density applications
-
Jun
-
M. Specht, R. Kommling, L. Dreeskornfeld, W. Weber, F. Hofmann, D. Alvarez, J. Kretz, R. J. Luyken, W. Rosner, H. Reisinger, E. Landgtaf, T. Schulz, J. Hartwich, M. Stadele, V. Klandievski, E. Hartmann, and L. Risch, "Sub-40 nm tri-gate charge trapping nonvolatile memory cells for high-density applications," in VLSI Symp. Tech. Dig., Jun. 2004, pp. 244-245.
-
(2004)
VLSI Symp. Tech. Dig
, pp. 244-245
-
-
Specht, M.1
Kommling, R.2
Dreeskornfeld, L.3
Weber, W.4
Hofmann, F.5
Alvarez, D.6
Kretz, J.7
Luyken, R.J.8
Rosner, W.9
Reisinger, H.10
Landgtaf, E.11
Schulz, T.12
Hartwich, J.13
Stadele, M.14
Klandievski, V.15
Hartmann, E.16
Risch, L.17
-
8
-
-
34247576814
-
Fully integrated SONOS flash memory cell array with BT-FinFET structure
-
S. K. Sung, T. Y. Kim, E. S. Cho, H. J. Cho, B. Y. Choi, C. W. Oh, B. G. Cho, C. H. Lee, and D. Park, "Fully integrated SONOS flash memory cell array with BT-FinFET structure," in IEEE Silicon Nanoworkshop, 2005, pp. 102-103.
-
(2005)
IEEE Silicon Nanoworkshop
, pp. 102-103
-
-
Sung, S.K.1
Kim, T.Y.2
Cho, E.S.3
Cho, H.J.4
Choi, B.Y.5
Oh, C.W.6
Cho, B.G.7
Lee, C.H.8
Park, D.9
-
9
-
-
46049105352
-
Multilevel p+ tri-gate SONOS NAND string arrays
-
C. Friederich, M. Specht, T. Lutz, F. Hofmann, L. Dreeskornfeld, W. Webber, J. Kretz, T. Melde, W. Rosner, E. Landgraf, J. Hartwich, M. Stadele, L. Risch, and D. Richter, "Multilevel p+ tri-gate SONOS NAND string arrays," in IEDM Tech. Dig., 2006, pp. 963-966.
-
(2006)
IEDM Tech. Dig
, pp. 963-966
-
-
Friederich, C.1
Specht, M.2
Lutz, T.3
Hofmann, F.4
Dreeskornfeld, L.5
Webber, W.6
Kretz, J.7
Melde, T.8
Rosner, W.9
Landgraf, E.10
Hartwich, J.11
Stadele, M.12
Risch, L.13
Richter, D.14
-
10
-
-
51949096070
-
Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory
-
K. H. Yeo, K. H. Cho, M. Li, S. D. Suk, Y. Y. Yeoh, M. S. Kim, H. Bae, J. M. Lee, S. K. Sung, J. Seo, B. Park, D. W. Kim, D. Park, and W. S. Lee, "Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOS NAND flash memory," in VLSI Symp. Technol., 2008, pp. 138-139.
-
(2008)
VLSI Symp. Technol
, pp. 138-139
-
-
Yeo, K.H.1
Cho, K.H.2
Li, M.3
Suk, S.D.4
Yeoh, Y.Y.5
Kim, M.S.6
Bae, H.7
Lee, J.M.8
Sung, S.K.9
Seo, J.10
Park, B.11
Kim, D.W.12
Park, D.13
Lee, W.S.14
-
11
-
-
46049100422
-
A multi-layer stackable thin-film transistor (TFT) NAND-type flash memory
-
session 2-4
-
E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A multi-layer stackable thin-film transistor (TFT) NAND-type flash memory," in IEDM Tech. Dig., 2006, pp. 41-44. session 2-4.
-
(2006)
IEDM Tech. Dig
, pp. 41-44
-
-
Lai, E.K.1
Lue, H.T.2
Hsiao, Y.H.3
Hsieh, J.Y.4
Lu, C.P.5
Wang, S.Y.6
Yang, L.W.7
Yang, T.8
Chen, K.C.9
Gong, J.10
Hsieh, K.Y.11
Liu, R.12
Lu, C.Y.13
-
12
-
-
49249101277
-
A study of gate-sensing and channel-sensing (GSCS) transient analysismethod: Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices
-
Aug
-
P. Y. Du, H. T. Lue, S. Y. Wang, T. Y. Huang, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A study of gate-sensing and channel-sensing (GSCS) transient analysismethod: Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices," IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 2229-2237, Aug. 2008.
-
(2008)
IEEE Trans. Electron Devices
, vol.55
, Issue.8
, pp. 2229-2237
-
-
Du, P.Y.1
Lue, H.T.2
Wang, S.Y.3
Huang, T.Y.4
Hsieh, K.Y.5
Liu, R.6
Lu, C.Y.7
-
13
-
-
10644273634
-
A transient analysis method to characterize the trap vertical location in nitride trapping device
-
Dec
-
H. T. Lue, Y. H. Shih, K. Y. Hsieh, R. Liu, and C. Y. Lu, "A transient analysis method to characterize the trap vertical location in nitride trapping device," IEEE Electron Device Lett., vol. 25, no. 12, pp. 816-818, Dec. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.12
, pp. 816-818
-
-
Lue, H.T.1
Shih, Y.H.2
Hsieh, K.Y.3
Liu, R.4
Lu, C.Y.5
-
14
-
-
33644633458
-
Temperature effects on trigate SOI MOSFETs
-
Mar
-
J. P. Colinge, L. Floyd, A. J. Quinn, G. Redmond, J. C. Alderman, W. Xiong, C. R. Cleavelin, T. Schulz, and K. Schruefer, "Temperature effects on trigate SOI MOSFETs," IEEE Electron Device Lett., vol. 27, no. 3, pp. 172-174, Mar. 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.3
, pp. 172-174
-
-
Colinge, J.P.1
Floyd, L.2
Quinn, A.J.3
Redmond, G.4
Alderman, J.C.5
Xiong, W.6
Cleavelin, C.R.7
Schulz, T.8
Schruefer, K.9
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