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Volumn 6921, Issue , 2008, Pages

Gate edge roughness in electron beam direct write and its influence to device characteristics

Author keywords

CD SEM metrology; Electrical characteristics; Electron beam direct write; Line edge roughness; Line width roughness; Power spectrum density

Indexed keywords

CD-SEM METROLOGY; ELECTRICAL CHARACTERISTIC; ELECTRON BEAM DIRECT WRITE; LINE EDGE ROUGHNESS; LINEWIDTH ROUGHNESS; POWER SPECTRUM DENSITY;

EID: 67149106314     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.772649     Document Type: Conference Paper
Times cited : (6)

References (12)
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    • Pain, L.1
  • 4
    • 3843130605 scopus 로고    scopus 로고
    • Effect of line edge roughness (LER) and line width roughness (LWR) on sub-100 nm device performance
    • Lee, Ji-Young et al., "Effect of line edge roughness (LER) and line width roughness (LWR) on sub-100 nm device performance", Proc. of SPIE 5376, 427-433 (2004).
    • (2004) Proc. of SPIE , vol.5376 , pp. 427-433
    • Lee, J.-Y.1
  • 5
    • 0036927513 scopus 로고    scopus 로고
    • Line edge roughness: Characterization, modeling and impact on device behavior
    • Croon, J. A., et al., "Line edge roughness: characterization, modeling and impact on device behavior", IEDM Tech. Dig., 307-310, 2002.
    • (2002) IEDM Tech. Dig. , pp. 307-310
    • Croon, J.A.1
  • 6
    • 35148867713 scopus 로고    scopus 로고
    • Advanced line edge roughness measurements application for mask metrology
    • Marschner, Thomas et al., "Advanced line edge roughness measurements application for mask metrology", Proc. of SPIE 6518, 65181R1-11 (2007).
    • (2007) Proc. of SPIE , vol.6518
    • Marschner, T.1
  • 7
    • 0033714120 scopus 로고    scopus 로고
    • Modeling line edge roughness effects in sub 100 nm gate length device
    • th SISPAD, 131-134 (2000).
    • (2000) th SISPAD , pp. 131-134
    • Oldiges, P.1
  • 8
    • 0035364688 scopus 로고    scopus 로고
    • An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
    • DOI 10.1109/55.924844, PII S0741310601046572
    • Diaz, Carlos H. et al., "An experimentally validated analytical model for gate line-edge roughness (LER) effects on technological scaling", IEEE Electron Device Letters 22(6), 287-289 (2001). (Pubitemid 32584997)
    • (2001) IEEE Electron Device Letters , vol.22 , Issue.6 , pp. 287-289
    • Diaz, C.H.1    Tao, H.-J.2    Ku, Y.-C.3    Yen, A.4    Young, K.5
  • 9
    • 4344596531 scopus 로고    scopus 로고
    • 193nm Resist roughness characterization and process propagation investigation using a CD-SEM
    • Marschner, Thomas et al., "193nm Resist roughness characterization and process propagation investigation using a CD-SEM", Proc. of SPIE 5375, 477-485 (2004).
    • (2004) Proc. of SPIE , vol.5375 , pp. 477-485
    • Marschner, T.1
  • 12
    • 10644264480 scopus 로고    scopus 로고
    • Experimental investigation of the impact of LWR on sub-100 nm device performance
    • Kim, Hyun-Woo et al., "Experimental investigation of the impact of LWR on sub-100 nm device performance", IEEE Trans. Electron Devices 51(12), 1984-1988 (2004).
    • (2004) IEEE Trans. Electron Devices , vol.51 , Issue.12 , pp. 1984-1988
    • Kim, H.-W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.