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Volumn 7271, Issue , 2009, Pages

Interference assisted lithography for patterning of 1D gridded design

Author keywords

Double exposure; Interference lithography; Regular design; SRAM

Indexed keywords

6T-SRAM; BITCELL; COST-EFFECTIVE SOLUTIONS; DESIGN RULES; DOUBLE EXPOSURE; ELECTRICAL CHARACTERISTIC; INTERFERENCE LITHOGRAPHY; LITHOGRAPHY SIMULATION; RANDOM LAYOUT; REGULAR DESIGN; SRAM;

EID: 65849222177     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.812033     Document Type: Conference Paper
Times cited : (26)

References (17)
  • 3
    • 62649139047 scopus 로고    scopus 로고
    • 32nm 1-D regular pitch SRAM bit-cell design for interference assisted lithography
    • Robert T. Greenway, Kwangok Jeong, Andrew B. Kahng, Chul-Hong Park, John S. Petersen, "32nm 1-D Regular Pitch SRAM Bit-cell Design for Interference Assisted Lithography", Proc. SPIE, Vol. 7122, 71221L (2008)
    • (2008) Proc. SPIE , vol.7122
    • Greenway, R.T.1    Jeong, K.2    Kahng, A.B.3    Park, C.-H.4    Petersen, J.S.5
  • 4
    • 43249083986 scopus 로고    scopus 로고
    • APF pitch halving for 22nm logic cells using gridded design rules
    • Michael C. Smayling, Christopher Bencher, Hao D. Chen, Huixiong Dai, Michael P. Duane, "APF pitch halving for 22nm logic cells using gridded design rules", Proc. SPIE, Vol. 6925, 6925 IE (2008)
    • (2008) Proc. SPIE , vol.6925
    • Smayling, M.C.1    Bencher, C.2    Chen, H.D.3    Dai, H.4    Duane, M.P.5
  • 7
    • 57849139558 scopus 로고    scopus 로고
    • 45nm design for manufacturing
    • Clair Webb, "45nm design for manufacturing", Intel Technology Journal, Vol. 12 (02), pp. 121-130 (2008)
    • (2008) Intel Technology Journal , vol.12 , Issue.2 , pp. 121-130
    • Webb, C.1
  • 10
    • 2942676779 scopus 로고    scopus 로고
    • Immersion lithography and its impact on semiconductor manufacturing
    • B.J. Lin, "Immersion lithography and its impact on semiconductor manufacturing," Proc. of SPIE, Vol. 5377 (2004).
    • (2004) Proc. of SPIE , vol.5377
    • Lin, B.J.1
  • 11
    • 65849359833 scopus 로고    scopus 로고
    • Gridded design rules - 1-D design enables scaling of CMOS logic
    • M. C. Smayling, "Gridded Design Rules - 1-D Design Enables Scaling of CMOS Logic," Nanochip Technology Journal, Vol.6(2), (2008).
    • (2008) Nanochip Technology Journal , vol.6 , Issue.2
    • Smayling, M.C.1
  • 12
    • 65849377081 scopus 로고    scopus 로고
    • Cell-based aerial image analysis of design styles for 45 nanometer generation logic
    • M. Smayling, "Cell-based aerial image analysis of design styles for 45 nanometer generation logic," Proc. of SPIE, Vol.6521 (2007).
    • (2007) Proc. of SPIE , vol.6521
    • Smayling, M.1
  • 16
    • 25144518123 scopus 로고    scopus 로고
    • An integrated imaging system for the 45-nm technology node contact holes using polarized OAI, immersion, weak PSM, and negative resists
    • DOI 10.1117/12.600010, 46, Optical Microlithography XVIII
    • J. S. Petersen, M. J. Maslow and R. T. Greenway, An Integrated Imaging System for the 45-nm Technology Node Contact Holes Using Polarized OAI, Immersion Weak PSM and Negative Resists, Proc. SPIE Optical Microlithography XVIII, 5754 (2005), pp. 488-497. (Pubitemid 41336177)
    • (2005) Proceedings of SPIE - the International Society for Optical Engineering , vol.5754 , Issue.PART 1 , pp. 488-497
    • Petersen, J.S.1    Maslow, M.J.2    Greenway, R.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.