Low k1 logic design using gridded design rules

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6925, Issue , 2008, Pages

  Smayling, Michael C ^a   Liu, Hua Yu ^b   Cai, Lynn ^b  

^a Tela Innovations Inc   (United States)

^b ASML US Inc   (United States)

Author keywords

Context dependent hotspots; Low k1 gridded design rules; Restricted design rules

Indexed keywords

DATA STRUCTURES; MASKS; PHOTOLITHOGRAPHY; TOPOLOGY; VERIFICATION;

RANDOM LOGIC FUNCTIONS; RESTRICTED DESIGN RULES (RDR);

LOGIC DESIGN;

EID: 43249089630     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.772875     Document Type: Conference Paper

References (8)

1. W. Arnold, "Lithography for the 32nm Technology Node," 2006 IEDM 32nm Technology Short Course.
2. L. Liebmann, "Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity?" ISPD 2003, Monterey, CA, USA.
3. L. Capodieci, "Layout Printability Verification and Physical Design Regularity: Roadmap Enablers for the next decade," EDPS 2006, Monterey, CA, USA.
4. M. Smayling, "Cell-based aerial image analysis of design styles for 45 nanometer generation logic," SPIE Microlithography 2007, San Jose, USA.
5. K. Koike, "OPC to reduce variability of transistor properties," SPIE Microlithography 2007, San Jose, USA.
6. D. Perry, "Model-based Approach for Design Verification and Co-optimization of Catastrophic and Parametric-related Defects due to Systematic Manufacturing Variations," SPIE Microlithography 2007, San Jose, USA.
7. R. Pack, "Physical and timing verification of subwavelength-scale designs: I. Lithography impact of MOSFETs," SPIE Microlithography 2003, Santa Clara, USA.
8. A. Skumanich, "Advanced etch applications using tool-level data," Solid State Technology, June, 2004. (http://sst.pennnet.com/ Articles/Article_Display.cfm?Section=ARTCL&ARTICLE_ID=26470amp;VERSION_NUM= 1&p=5