Testing and evaluation of silicon die strength

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 30, Issue 2, 2007, Pages 106-114

  Tsai, Ming Yi ^a   Lin, C S ^a,b  

^a CHANG GUNG UNIVERSITY   (Taiwan)

^b Phoenix Precision Technology Corporation   (Taiwan)

Author keywords

Die chipping; Die strength; Electronic packaging; Failure modes; Fatigue strength; Test methods

Indexed keywords

3-D PACKAGES; ARTIFICIAL CRACKS; AXIAL STRESS; CUTTING PROCESS; DIE STRENGTH; EDGE CHIPPING; EDGE CRACKS; ELECTRONIC PACKAGING; FAILURE SURFACES; FATIGUE STRENGTH; GRINDING MARKS; GROUND SURFACES; IC CHIPS; LINE-LOAD TESTS; LOAD TESTS; LOADING CONDITIONS; PLATE-ON-ELASTIC-FOUNDATION TESTS; SILICON DIES; STACKED DIE PACKAGES; STRESS FIELDS; STRESS STATE; SURFACE CONDITIONS; TEMPERATURE LOADINGS; TEST METHODS; TESTING AND EVALUATIONS;

CHIP SCALE PACKAGES; CRACK INITIATION; CRACKS; CRYSTAL CUTTING; CRYSTAL LATTICES; ELECTRONIC EQUIPMENT MANUFACTURE; FAILURE MODES; FATIGUE OF MATERIALS; FATIGUE TESTING; GRINDING (COMMINUTION); GRINDING (MACHINING); LOADS (FORCES); NONMETALS; RELIABILITY ANALYSIS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; STRESS CORROSION CRACKING; SURFACE PROPERTIES; SURFACE ROUGHNESS; TESTING;

DIES;

EID: 65449130789     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2007.899072     Document Type: Article

References (8)

1. T. Y. Wu, Y. Tsukada, and W. T. Chen, "Materials and mechanics issues in flip-chip organic packaging," in Proc. 46th Electron. Compon. Technol. Conf., Jun. 1996, pp. 524-533.
2. K. Hu, C. P. Yeh, B. Doot, A. F. Skipor, and K. W. Wyatt, "Die cracking in flip chip on board assembly," in Proc. 45th Electron. Compon. Technol. Conf., May 1995, pp. 293-299.
3. M. Y. Tsai, C. H. Hsu, and C. T. Wang, "Investigation of thermomechanical behaviors of flip chip BGA in IC packaging," IEEE Trans. Compon. Packag. Technol., vol. 27, no. 3, pp. 568-576, Sep. 2004.
4. B. H. Yeung, V. Hause, and T. Y. T. Lee, "Assessment of backside processes through die strength evaluation," IEEE Trans. Adv. Packag. vol. 23, no. 3, pp. 582-587, Aug. 2000.
5. B. H. Yeung and T. Y. T. Lee, "An overview of experimental methodologies and their applications for die strength measurement," IEEE Trans. Compon. Packag. Technol., vol. 26, no. 2, pp. 423-428, Jun. 2003.
6. B. Cotterell, Z. Chen, J. B. Han, and N. X. Tan, "The strength of the silicon die in flip-chip assemblies," ASME J. Electron. Packag., vol. 125, pp. 114-119, Mar. 2003.
7. N. McLellan, N. Fan, S. Liu, K. Lau, and J. Wu, "Effect of wafer thinning condition on the roughness, morphology and fracture strength of silicon die," ASME J. Electron. Packag., vol. 126, pp. 110-114, 2004.
8. L. L. Mercado and V. Sarihan, "Evaluation of die edge cracking in flip-chip PBGA packages," IEEE Trans. Compon. Packag. Technol., vol. 26, no. 4, pp. 719-723, Dec. 2003.