Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 2, 2008, Pages 151-155

  Meher, Pramod Kumar ^a   Mohanty, Basant Kumar ^b   Patra, Jagdish Chandra ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b JAYPEE UNIVERSITY OF ENGINEERING AND TECHNOLOGY   (India)

Author keywords

2 dimensional (2 D) DWT; Discrete wavelet transform (DWT); Systolic array; VLSI

Indexed keywords

DIGITAL STORAGE; DISCRETE WAVELET TRANSFORMS; SYSTOLIC ARRAYS;

2-DIMENSIONAL (2-D) DWT; DURATION OF CYCLES; EFFICIENT IMPLEMENTATION; HARDWARE COMPLEXITY; MODULAR ARCHITECTURES; TWO DIMENSIONAL (2 D); TWO-DIMENSIONAL DISCRETE WAVELET TRANSFORM; VLSI;

SIGNAL RECONSTRUCTION;

EID: 64849098678     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.911801     Document Type: Article

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