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Volumn 14, Issue 3, 2003, Pages 217-231

Systolic array architectures for computation of the discrete wavelet transform

Author keywords

Discrete wavelet transform; Systolic array architecture; VLSI

Indexed keywords

COMPUTATIONAL METHODS; ONE DIMENSIONAL; SIGNAL FILTERING AND PREDICTION; SYSTOLIC ARRAYS; TWO DIMENSIONAL; WAVELET TRANSFORMS;

EID: 0041317795     PISSN: 10473203     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1047-3203(03)00004-X     Document Type: Article
Times cited : (7)

References (18)
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  • 4
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    • VLSI architecture for the discrete wavelet transform
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    • Why systolic architectures?
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    • Kung, H.T.1
  • 8
    • 0003859414 scopus 로고
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    • (1988) VLSI Array Processors
    • Kung, S.Y.1
  • 9
    • 0000014566 scopus 로고
    • An efficient systolic architecture for the one-dimensional wavelet transform
    • Orlando, FL
    • Lang, R., Plesner, E., Schöder, H., Spray, A., 1994. An efficient systolic architecture for the one-dimensional wavelet transform. Proc. SPIE Wavelet Appl. 2242, Orlando, FL, 925-935.
    • (1994) Proc. SPIE Wavelet Appl. , vol.2242 , pp. 925-935
    • Lang, R.1    Plesner, E.2    Schöder, H.3    Spray, A.4
  • 10
    • 0009576223 scopus 로고
    • Parallel implementation of wavelet decomposition/reconstruction algorithms
    • Orlando, FL
    • Lee, H.J., Liu, J.C., Chan, A.K., Chui, C.K., 1994. Parallel implementation of wavelet decomposition/reconstruction algorithms. Proc. SPIE Wavelet Appl. 2242, Orlando, FL, 248-259.
    • (1994) Proc. SPIE Wavelet Appl. , vol.2242 , pp. 248-259
    • Lee, H.J.1    Liu, J.C.2    Chan, A.K.3    Chui, C.K.4
  • 11
    • 0026084572 scopus 로고
    • VLSI architecture for 2-D Daubechies wavelet transform without multipliers
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  • 12
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  • 14
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.