Optimal memory organization for scalable texture codecs in MPEG-4

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 9, Issue 2, 1999, Pages 218-243

  Lafruit, Gauthier ^a   Nachtergaele, Lode ^a   Bormans, Jan ^a   Engels, Marc ^a   Bolsens, Ivo ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANIMATION; COSINE TRANSFORMS; DATA HANDLING; DATA STORAGE EQUIPMENT; DECODING; IMAGE COMPRESSION; MULTIMEDIA SYSTEMS; VLSI CIRCUITS; WAVELET TRANSFORMS;

MPEG 4; STILL TEXTURE CODING; ZERO TREE WAVELET CODING;

IMAGE CODING;

EID: 0033099266     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.752091     Document Type: Article

References (27)

1. B. Gordon, E. Tsern, and T. Meng, "Design of a low power video decompression chip set for portable applications," J. VLSI Signal Process. Syst., no. 13, pp. 125-142, 1996.
2. T. H. Meng, B. M. Gordon, E. K. Tsern, and A. C. Hung, "Portable video-on-demand in wireless communication," Proc. IEEE, vol. 83, pp. 659-680, Apr. 1995.
3. L. Nachtergaele, F. Catthoor, B. Kapoor, S. Janssens, and D. Moolenaar, "Low power data transfer and storage exploration for H.263 video decoder system," IEEE J. Select. Areas Commun., vol. 16, pp. 1-9, Jan. 1998.
4. _, "Low power storage exploration for H.263 video decoder," in Proc. IEEE Workshop VLSI Signal Processing, San Francisco, CA, Oct. 1996. pp. 115-124.
5. MPEG. (1999). ISO/IEC JTC1/SC29 WG11. [Online]. Available: http://drogo.cselt.stet.it/mpeg/.
6. L. Nachtergaele, T. Gijbels, J. Bormans, F. Catthoor, and M. Engels, "Power and speed-efficient code transformation of multimedia algorithms for RISC processor implementation," in Proc. IEEE Workshop Multimedia Signal Processing, Los Angeles, CA, Dec. 7-9, 1998.
7. R. Glidden, Graphics Programming with Direct3D: Techniques and Concepts. Reading, MA: Addison-Wesley, 1997, pp. 48-51.
8. "Coding of audio-visual objects: Visual," ISO/IEC 14496-2 committee draft, JTC1/SC29/WG11/MPEG97/N1902, Fribourg, Germany, Oct. 1997.
9. T. Suzuki and Y. Yagasaki, "The results of CE V2: Results of spatial and quality scalability," ISO/IEC JTC1/SC29/WG11/m2437, Stockholm, Sweden, July 1997.
10. P. J. Burt and E. H. Adelson, "The Laplacian pyramid as a compact image code," IEEE Trans. Commun., vol. 31, pp. 532-540, Apr. 1983.
11. J. M. Shapiro, "Embedded image coding using the zerotrees of wavelet coefficients," IEEE Trans. Image Processing, vol. 41, pp. 3445-3462, Dec. 1993.
12. W. Sweldens. (1994). The lifting scheme: A custom-design construction of biorthogonal wavelets. [Online]. Available FTP: ftp.math.sc.edu/pub/imi_94.
13. _, "The lifting scheme: A new philosophy in biorthogonal wavelet constructions," in Proc. SPIE Conf., 1995, vol. 2569, pp. 68-79.
14. W. Sweldens and I. Daubechies, "Factoring wavelet transforms into lifting steps," AT&T Tech. Rep. BL0112170-960927-20TM, Murray Hill and Princeton, NJ, Sept. 1996.
15. C. Chakrabarti, M. Vishwanath, and R. Owens, "Architectures for wavelet transforms," in Proc. VLSI Signal Processing VI, New York, 1993, pp. 507-515.
16. G. Knowles, "VLSI architecture for the discrete wavelet transform," Electron. Lett., vol. 26, no. 15, pp. 1184-1185, July 1990.
17. K. K. Parhi and T. Nishitani, "Folded VLSI architectures for discrete wavelet transforms," in Proc. IEEE Int. Symp. Circuits and Systems, Chicago, IL, 1993, pp. 1734-1737.
18. _, "VLSI architectures for discrete wavelet transforms," IEEE Trans. VLSI Syst., vol. 1, pp. 191-202, June 1993.
19. M. Vishwanath, "The recursive pyramid algorithm for the discrete wavelet transform," IEEE Trans. Signal Processing, vol. 42, pp. 673-676, Mar. 1994.
20. M. Vishwanath and C. Chakrabarti, "A VLSI architecture for real-time hierarchical encoding/decoding of video using the wavelet transform," in Proc. Int. Conf. Acoustics, Speech and Signal Processing, Adelaide, Australia, Apr. 1994, pp. II-401-II-404.
21. R. Lang and A. Spray, "Input buffering requirements of a systolic array for the inverse discrete wavelet transform," in Proc. Int. Conf. Application Specific Array Processors, Los Alamitos, CA, 1995, pp. 166-173.
22. K. K. Parhi, "Architectures for lattice structure based orthonormal discrete wavelet transform," in Proc. Int. Conf. Application Specific Array Processors, San Francisco, CA, Aug. 1994, pp. 259-271.
23. T. C. Denk and K. K. Parhi, "Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing," in Proc. IEEE Int. Symp. Circuit and Systems, London, England, May 1994, vol. 3, pp. 77-80.
24. G. Lafruit and J. Bormans, "Complexity comparison between scalable wavelet codec and scalable DCT codec," ISO/IEC JTC1/SC29/WG11/MPEG97/m2654, Fnbourg, Germany, Oct. 1997.
25. _, "Graceful degradation parameters for a scalable wavelet codec," ISO/IEC JTC1/SC29/WG11/MPEG97/m2655, Fribourg, Germany, Oct. 1997.
26. G. Lafruit, F. Catthoor, J. Cornelis, and H. De man, "An efficient VLSI architecture for the 2-D wavelet transform with novel image scan," IEEE Trans. VLSI Syst., to be published.
27. G. Lafruit and J. Cornelis, "A space-filling curve image scan for low power VLSI implementation of wavelet coding," in Applied Signal Processing. London, U.K.: Springer-Verlag, 1995, vol. 2, pp. 87-107.