Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

IEEE Transactions on Signal Processing

Volumn 53, Issue 4, 2005, Pages 1575-1586

  Huang, Chao Tsung ^a   Tseng, Po Chih ^a   Chen, Liang Gee ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

B spline factorization; Discrete wavelet transform; Lifting scheme; Line based method; VLSI architecture

Indexed keywords

COMPUTATIONAL COMPLEXITY; CONVOLUTION; HIGH PASS FILTERS; LOW PASS FILTERS; MATRIX ALGEBRA; WAVELET TRANSFORMS;

B-SPLINE FACTORIZATION; DISCRETE WAVELET TRANSFORM; LIFTING SCHEME; LINE-BASED METHOD; VLSI ARCHITECTURE;

SIGNAL PROCESSING;

EID: 17444408839     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2005.843704     Document Type: Article

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