Ion implant:A new enabler for 32nm and 22nm devices

Solid State Technology

Volumn 52, Issue 3, 2009, Pages

  Kawski, James ^a   Merrill, Mark ^a  

^a VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL DAMAGES; DEVICE DESIGNS; DEVICE ISOLATIONS; DEVICE-SCALING; DOPANT DISTRIBUTIONS; DOPANT PROFILES; ION IMPLANTS; JUNCTION DEPTHS; LOW POWER TRANSISTORS; PERFORMANCE IMPROVEMENTS; POWER CONSUMPTION; PROCESS SIMPLIFICATIONS; SHALLOW JUNCTIONS; THERMAL BUDGETS;

POWER ELECTRONICS;

INNOVATION;

EID: 64849093341     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (8)

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5. T. Yamashita, M. Kitazanwa, Y. Kawasaki, H. Takashino, T. Kuroi, Y. Inoue, M. Inuishi, "Advanced Retrograde Well Technology for 90nm Node Embedded SRAM by High-Energy Parallel Beam" Japanese Jour. ofAppl. Phys., Part 1 41(4B), pp. 2399-403, 2002.
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8. C.R. Moon, J.J. Jung, D.W. Kwon, J.R. Yoo, D.H. Lee, K. Kim, "Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors," IEEE Elect. Dev. Lett., VOL. 28, NO. 2, pp. 114-116, 2007.