Effects of multithreading on cache performance

IEEE Transactions on Computers

Volumn 48, Issue 2, 1999, Pages 176-184

  Kwak, Hantak ^b   Lee, Ben ^a,b   Hurson, Ali R ^a,c   Yoon, Suk Han ^a,d   Hahn, Woo Jong ^a,d  

^a IEEE

^b Oregon State University   (United States)

^c The Pennsylvania State University   (United States)

^d Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

Context switching, and locality; Memory latency; Memory tolerance; Multithreading

Indexed keywords

MULTIPROGRAMMING; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

CONTEXT SWITCHING; MULTITHREADED VIRTUAL PROCESSOR (MVP) MODELS; MULTITHREADING;

BUFFER STORAGE;

EID: 0033075285     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.752659     Document Type: Article

References (25)

1. A. Agarwal, J. Kubiatowicz, D. Kranz, and B. Lim, "Sparcle: An Evolutionary Processor Design for Large-Scale Multiprocessors," IEEE Micro, pp. 48-61, June 1993.
2. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith, "The Tera Computer System," Proc. Int'l Conf. Supercomputing, pp. 1-6, June 1990.
3. D. Butenhof, Programming with POSIX Threads. Addison Wesley, 1997.
4. D. Callahan, K. Kennedy, and A. Porterfield, "Software Prefetching," Proc. Fourth Symp. Architectural Support for Programming Languages and Operating Systems, pp. 40-52, Apr. 1991.
5. B. Catanzaro, Multiprocessor System Architectures. Prentice Hall, 1994.
6. T. Chen and J. Baer, "A Performance Study of Software and Hardware Data Prefetching Schemes," Proc. 21st Ann. Int'l Symp. Computer Architecture, pp. 223-232, Apr. 1994.
7. S. Coleman and K. McKinley, "Tile Size Selection Using Cache Organization and Data Layout," Proc. SIGPLAN '95 Conf. Programming Language Design and Implementation, June 1995.
8. D. Culler and J. Singh, Parallel Computer Architecture: A Hardware/ Software Approach. Morgan Kaufmann, 1999.
9. H. Gulati and N. Bagherzadeh, "Performance Study of a Multithreaded Superscalar Microprocessor," Proc. Second Int'l Symp. High-Performance Computer Architecture, pp. 298-307, Jan. 1995.
10. B. Gunther, "Multithreading with Distributed Functional Units," IEEE Trans. Computers, vol. 46, no. 4, pp. 399-411, Apr. 1997.
11. J. Hennessy and D. Patterson, Computer Architecture - A Quantitative Approach, second ed. Morgan Kaufmann, 1994.
12. T. Johnson, M. Merten, and W. Hwu, "Runtime Spatial Locality Detection and Optimization," Proc. Micro-30, Dec. 1997.
13. A. Klaiber and H. Levy, "An Architecture for Software-Controlled Data Prefetching," Proc. 18th Ann. Int'l Symp. Computer Architecture, pp. 43-53, May 1991.
14. G. Kurpanek, K. Chan, J. Zheng, E. DeLano, and W. Bryg, "PA7200: A PA-RISC Processor with Integrated High Performance MP Bus Interface," Digest of Papers, Spring COMPCON '94, pp. 375-382, 1994.
15. B. Lee, H. Kwak, R. Carlson, S. Yoon, and W. Ran, "A Simulation Study of Multithreaded Virtual Processor," Proc. Second European Conf. Parallel and Distributed Systems, July 1998.
16. J. Lo, S. Eggers, J. Emer, H. Levy, R. Stamm, and D. Tullsen, "Converting Thread-Level Parallelism into Instruction-Level Parallelism via Simultaneous Multithreading," ACM Trans. Computer Systems, pp. 322-354, Aug. 1997.
17. A. Milenkovic and V. Milutinovic, "Lazy Prefetching," Proc. IEEE HICSS-98, Jan. 1998.
18. V. Milutinovic, M. Tomasevic, B. Markovic, and M. Tremblay, "The Split Temporal/Spatial Cache: Initial Performance Analysis," Proc. SCIzzL-5, Mar. 1996.
19. T. Mowry, M. Lam, and A. Gupta, "Design and Evaluation of a Compiler Algorithm for Prefetching," Proc. Fifth Int'l Conf. Architectural Support for Programming Language and Operating Systems, pp. 62-73 Oct. 1992.
20. S. Palacharla and R. Kessler, "Evaluating Stream Buffers as a Second Cache Replacement," Proc. 21st Ann. Int'l Symp. Computer Architecture, pp. 24-33, Apr. 1994.
21. J. Philbin, J. Edler, O. Anshus, C. Douglas, and K. Li, "Thread Scheduling for Cache Locality," Proc. Architectural Support for Programming Languages and Operating Systems, pp. 60-71, 1996.
22. B. Smith, "The Architecture of HEP," Proc. Parallel MIMD Computation: HEP Supercomputer and Applications, 1985.
23. G. Sohi and M. Franklin, "High-Bandwidth Data Memory Systems for Superscalar Processors," Proc. AS-PLOS-IV, pp. 53-62, Apr. 1991.
24. R. Thekkath and S. Eggers, "The Effectiveness of Multiple Hardware Contexts," Proc. Int'l Conf. Architectural Support for Programming Languages and Operating Systems, Oct. 1994.
25. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta, "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. 22nd Int'l Symp. Computer Architecture, pp. 24-36, June 1995.