A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Chang, Hsiang Hui ^a   Sun, Chih Hao ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL FILTERS; ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; INTEGRATED CIRCUIT MANUFACTURE; JITTER; TIMING CIRCUITS;

CHARGE PUMP CIRCUIT; DELAY LOCKED LOOP; DIFFERENTIAL-TO-SINGLE-ENDED CONVERTER; LOCK DETECTOR; MISMATCH-INDUCED TIMING ERROR; MULTIPHASE CLOCK; PHASE DETECTOR;

PHASE LOCKED LOOPS;

EID: 0038306218     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. C. H. Park, O. Kim, and B. Kim, "A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching," IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 777-783, May 2001.
2. L. Wu, W. C. B. Jr., "A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications," ISSCC Dig. Tech. Papers, pp. 396-399, 2001.
3. G. Chien and P. R. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996-1999, Dec. 2000