-
1
-
-
47249121842
-
Silicon nanowire field effect devices by top-down CMOS technology. device research conference 65th DRC
-
Balasubramanian, N.; Singh, N.; Rustagi, S. C.; Kavitha; Agarwal, A.; Gao, Z. Q.; Lo, G. Q.; Kwong, D. L. Silicon Nanowire Field Effect Devices By Top-Down CMOS Technology. Device Research Conference, 65th DRC, Conference Digest; 2007, pp 47-48.
-
(2007)
Conference Digest
, pp. 47-48
-
-
Balasubramanian, N.1
Singh, N.2
Rustagi, S.C.3
Kavitha Agarwal, A.4
Gao, Z.Q.5
Lo, G.Q.6
Kwong, D.L.7
-
3
-
-
0033329310
-
Sub 50-nm FinFET: PMOS
-
Huang, X.; Lee, W. C.; Kuo, C.; Hisamoto, D.; Chang, L.; Kedzierski, J.; Anderson, E.; Takeuchi, H.; Choi, Y. K.; Asano, K.; Subramanian, V.; King, T. J.; Bokor, J.; Hu, C. Sub 50-nm FinFET: PMOS. Tech. Dig.-Int. Electron Devices Meet. 1999, 67-70. (Pubitemid 30574416)
-
(1999)
Technical Digest - International Electron Devices Meeting
, pp. 67-70
-
-
Huang Xuejue1
Lee Wen-Chin2
Kuo Charles3
Hisamoto Digh4
Chang Leland5
Kedzierski Jakub6
Anderson Erik7
Takeuchi Hideki8
Choi Yang-Kyu9
Asano Kazuya10
Subramanian Vivek11
King Tsu-Jae12
Bokor Jeffrey13
Hu Chenming14
-
4
-
-
46049119669
-
Ultra-narrow silicon nanowire gate-all- Around CMOS devices: Impact of diameter. Channel-orientation and low temperature on device Performance
-
Singh, N.; Lim, F. Y.; Fang, W. W.; Rustagi, S. C.; Bera, L. K.; Agarwal, A.; Tung, C. H.; Hoe, K. M.; Omampuliyur, S. R.; Tripathi1, D.; Adeyeye1, A. O.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L. Ultra-Narrow Silicon Nanowire Gate-All- Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance. Tech. Dig.-Int. Electron Devices Meet. 2006, 547-550.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 547-550
-
-
Singh, N.1
Lim, F.Y.2
Fang, W.W.3
Rustagi, S.C.4
Bera, L.K.5
Agarwal, A.6
Tung, C.H.7
Hoe, K.M.8
Omampuliyur, S.R.9
Tripathi, D.10
Adeyeye, A.O.11
Lo, G.Q.12
Balasubramanian, N.13
Kwong, D.L.14
-
5
-
-
46049102044
-
Gate-All-Around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires
-
Yeo, K. H.; Suk, S. D.; Li, M.; Yeoh, Y. Y.; Cho, K. H.; Hong, K. H.; Yun, S.; Lee, M. S.; Cho, N.; Lee, K.; Hwang, D.; Park, B.; Kim, D. W.; Park, D.; Ryu, B. Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires. Tech. Dig.-Int. Electron Devices Meet. 2006, 539-542.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 539-542
-
-
Yeo, K.H.1
Suk, S.D.2
Li, M.3
Yeoh, Y.Y.4
Cho, K.H.5
Hong, K.H.6
Yun, S.7
Lee, M.S.8
Cho, N.9
Lee, K.10
Hwang, D.11
Park, B.12
Kim, D.W.13
Park, D.14
Ryu, B.15
-
6
-
-
46049117875
-
Advanced FinFET CMOS Technology: TiN-Gate fin-height control and asymmetric gate insulator thickness 4T-FinFETs
-
Liu, Y.; Matsukawa, T.; Endo, K.; Masahara, M.; Ishii, K.; O'uchi, S. I.; Yamauchi, H.; Tsukada, J.; Ishikawa, Y.; Suzuki, E. Advanced FinFET CMOS Technology: TiN-Gate, Fin-Height Control and Asymmetric Gate Insulator Thickness 4T-FinFETs. Tech. Dig.-Int. Electron Devices Meet. 2006, 989-992.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 989-992
-
-
Liu, Y.1
Matsukawa, T.2
Endo, K.3
Masahara, M.4
Ishii, K.5
O'uchi, S.I.6
Yamauchi, H.7
Tsukada, J.8
Ishikawa, Y.9
Suzuki, E.10
-
7
-
-
46049084627
-
A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET Utilizing Si (110) channel for both N and PMOSFETs
-
Kang, C. Y.; Choi, R.; Song, S. C.; Choi, K.; Ju, B. S.; Hussain, M. M.; Lee, B. H.; Bersuker, G.; Young, C.; Heh, D.; Kirsch, P.; Barnet, J.; Yang, J. W.; Xiong, W.; Tseng, H. H.; Jammy, R. A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET Utilizing Si (110) Channel for Both N and PMOSFETs. Tech. Dig.-Int. Electron Devices Meet. 2006, 885-888.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 885-888
-
-
Kang, C.Y.1
Choi, R.2
Song, S.C.3
Choi, K.4
Ju, B.S.5
Hussain, M.M.6
Lee, B.H.7
Bersuker, G.8
Young, C.9
Heh, D.10
Kirsch, P.11
Barnet, J.12
Yang, J.W.13
Xiong, W.14
Tseng, H.H.15
Jammy, R.16
-
8
-
-
46249091622
-
Three dimensionally stacked SiGe nanowire array and gate-all-around p- MOSFETs
-
Bera, L. K.; Nguyen, H. S.; Singh, N.; Liow, T. Y.; Huang, D. X.; Hoe, K. M.; Tung, C. H.; Fang, W. W.; Rustagi, S. C.; Jiang, Y.; Lo, G. Q.; Balasubramanian, N.; Kwong, D. L. Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p- MOSFETs. Tech. Dig.-Int. Electron Devices Meet. 2006, 551-554.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 551-554
-
-
Bera, L.K.1
Nguyen, H.S.2
Singh, N.3
Liow, T.Y.4
Huang, D.X.5
Hoe, K.M.6
Tung, C.H.7
Fang, W.W.8
Rustagi, S.C.9
Jiang, Y.10
Lo, G.Q.11
Balasubramanian, N.12
Kwong, D.L.13
-
9
-
-
46049086980
-
2/TiN gate stack
-
2/TiN Gate Stack. Tech. Dig.-Int. Electron Devices Meet. 2006, 997-1000.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 997-1000
-
-
Ernst, T.1
Dupré, C.2
Isheden, C.3
Bernard, E.4
Ritzenthaler, R.5
Maffini-Alvaro, V.6
Barbé, J.C.7
De Crecy, F.8
Toffoli, A.9
Vizioz, C.10
Borel, S.11
Andrieu, F.12
Delaye, V.13
Lafond, D.14
Rabillé, G.15
Hartmann, J.M.16
Rivoire, M.17
Guillaumot, B.18
Suhm, A.19
Rivallin, P.20
Faynot, O.21
Ghibaudo, G.22
Deleonibus, S.23
more..
-
10
-
-
46049089837
-
Doubling or quadrupling MuGFET Fin Integration scheme with higher pattern fidelity. Lower CD variation and higher layout efficiency
-
Rooyackers, R.; Augendre, E.; Degroote, B.; Collaert, N.; Nackaerts, A.; Dixit, A.; Vandeweyer, T.; Pawlak, B.; Ercken, M.; Kunnen, E.; Dilliway, G.; Leys, F.; Loo, R.; Jurczak, M.; Biesemans, S. Doubling or Quadrupling MuGFET Fin Integration Scheme with Higher Pattern Fidelity, Lower CD Variation and Higher Layout Efficiency. Tech. Dig.-Int. Electron Devices Meet. 2006, 993-996.
-
(2006)
Tech. Dig.-Int. Electron Devices Meet
, pp. 993-996
-
-
Rooyackers, R.1
Augendre, E.2
Degroote, B.3
Collaert, N.4
Nackaerts, A.5
Dixit, A.6
Vandeweyer, T.7
Pawlak, B.8
Ercken, M.9
Kunnen, E.10
Dilliway, G.11
Leys, F.12
Loo, R.13
Jurczak, M.14
Biesemans, S.15
-
11
-
-
34248186650
-
Silicon nanowire arrays for label-free detection of DNA
-
DOI 10.1021/ac061808q
-
Gao, Z. Q.; Agarwal, A.; Trigg, A. D.; Singh, N.; Fang, C.; Tung, C. H.; Fan, Y.; Buddharaju, K.; Kong, J. M. Silicon Nanowire Arrays for Label-Free Detection of DNA. Anal. Chem. 2007, 79, 3291-3297. (Pubitemid 46717159)
-
(2007)
Analytical Chemistry
, vol.79
, Issue.9
, pp. 3291-3297
-
-
Gao, Z.1
Agarwal, A.2
Trigg, A.D.3
Singh, N.4
Fang, C.5
Tung, C.-H.6
Fan, Y.7
Buddharaju, K.D.8
Kong, J.9
-
12
-
-
47249094618
-
Towards vertical III-V nanowire devices on silicon
-
Bakkers, E. P. A. M.; Borgstrom, M. T.; van den Einden, W.; van Weert, M.; Minot, E. D.; Kelkensberg, F.; van Kouwen, M.; van Dam, J. A.; Kouwenhoven, L. P.; Helman, V. Z. A.; Wunnicke, O.;Verheijen, M. A. Towards Vertical III-V Nanowire Devices on Silicon. Device Research Conference, 65th DRC, Conference Digest; 2007, pp 163-164.
-
(2007)
Device Research Conference, 65th DRC, Conference Digest
, pp. 163-164
-
-
Bakkers, E.P.A.M.1
Borgstrom, M.T.2
Van Den Einden, W.3
Van Weert, M.4
Minot, E.D.5
Kelkensberg, F.6
Van Kouwen, M.7
Van Dam, J.A.8
Kouwenhoven, L.P.9
Helman, V.Z.A.10
Wunnicke, O.11
Verheijen, M.A.12
-
13
-
-
47249154907
-
Impact ionization FETs based on silicon nanowires
-
Bjork, M. T.; Hayden, O.; Knoch, J.; Riel, H.; Schmid, H.; Riess, W. Impact Ionization FETs Based on Silicon Nanowires. Device Research Conference, 65th DRC, Conference Digest; 2007, pp 171-172.
-
(2007)
Device Research Conference 65th DRC Conference Digest
, pp. 171-172
-
-
Bjork, M.T.1
Hayden, O.2
Knoch, J.3
Riel, H.4
Schmid, H.5
Riess, W.6
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