Three dimensionally stacked sige nanowire array and gate-ail-around p-MOSFETs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2006, Pages

  Bera, L K ^a,b   Nguyen, H S ^a   Singh, N ^a   Liow, T Y ^a   Huang, D X ^a   Hoe, K M ^a   Tung, C H ^a   Fang, W W ^a   Rustagi, S C ^a   Jiang, Y ^a   Lo, G Q ^a   Balasubramanian, N ^a   Kwong, D L ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b SILTERRA MALAYSIA SDN BHD   (Malaysia)

Author keywords

[No Author keywords available]

Indexed keywords

(E ,3E) PROCESS; AND GATES; CMOS COMPATIBLE; EXCELLENT PERFORMANCE; INTERNATIONAL (CO); MOSFETS; NANOWIRE ARRAYS; NOVEL METHODS;

EID: 46249091622     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2006.346841     Document Type: Conference Paper

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