Estimating Circuit Activity in Combinational CMOS Digital Circuits

IEEE Design and Test of Computers

Volumn 17, Issue 2, 2000, Pages 112-119

  Soeleman, Hendrawan ^a,e   Roy, Kaushik ^b,c   Chou, Tan Li ^d  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

^c United States of America   (United States)

^d INTEL CORPORATION   (United States)

^e PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0346479458     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.844340     Document Type: Article

References (10)

1. F. Najm, "A Survey of Power Estimation Techniques in VLSI Circuits," IEEE Trans. VLSI Systems, Dec. 1994, pp. 446-455.
2. F. Najm, "Transition Density, a New Measure of Activity in Digital Circuits," IEEE Trans. Computer-Aided Design, Vol. 12, No. 2, Feb. 1993, pp. 310-323.
3. T.L. Chou, K. Roy, and S. Prasad, "Estimation of Circuit Activity Considering Signal Correlation and Simultaneous Switching," Proc. IEEE Int'l Conf. Computer-Aided Design, 1994, pp. 300-303.
4. R. Marculescu, D. Marculescu, and M. Pedram, "Switching Activity Analysis Considering Spatiotemporal Correlations," IEEE Trans. Computer-Aided Design of Integrated Circuits & Systems, 1994, pp. 294-299.
5. Z. Chen et al., "Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks," Proc. Int'l Symp. Low Power Electronics and Design, 1998, pp. 239-244.
6. K.P. Parker and E.J. McCluskey, "Probabilistic Treatment of General Combinatorial Networks," IEEE Trans. Computers, Vol. 24, June 1975, pp. 668-670.
7. K. Roy and S. Prasad, "Circuit Activity Based Logic Synthesis for Low Power Reliable Operations," IEEE Trans. VLSI Systems, Dec. 1993, pp. 503-513.
8. H. Soeleman, "Power Estimation of Static CMOS Combinational Digital Logic Circuit," master's thesis, Purdue University, 1996.
9. R. Burch et al., "A Monte Carlo Approach for Power Estimation," IEEE Trans. VLSI Systems, Vol. 1, No. 1, Mar. 1993, pp. 63-71.
10. F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. IEEE Int'l Symp. Circuits and Systems, June 1985, pp. 695-698.