Adaptive delay estimation for partitioning-driven PLD placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 1, 2003, Pages 60-63

  Hutton, Michael ^a   Adibsamii, Khosrow ^a   Leaver, Andrew ^a  

^a ALTERA CORPORATION   (United States)

Author keywords

Field programmable gate arrays (FPGAs); Programmable logic; Programmable logic devise (PLD); Timing driven placement

Indexed keywords

ALGORITHMS; APPROXIMATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DEVICES;

PROGRAMMABLE LOGIC DEVICES (PLD);

VLSI CIRCUITS;

EID: 0037316907     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.808424     Document Type: Article

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