Design and performance analysis of a nanoscaled inverter based on wrap-around-gate nanowire MOSFETs

Micro and Nano Letters

Volumn 4, Issue 1, 2009, Pages 16-21

  Seyedi, A ^c   Pavel, A A ^a   Sharma, A K ^b   Islam, N E ^a  

^a University of Missouri   (United States)

^b AIR FORCE RESEARCH LABORATORY   (United States)

^c University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL INVERTERS; CURRENT DRIVES; GATE LENGTHS; INVERTER-BASED; LONG-CHANNEL DEVICES; MOSFETS; NANO CHANNELS; NANOSCALED; NANOWIRE MOSFETS; PERFORMANCE ANALYSIS; POWER CONSUMPTION; RISE TIME; SILICON NANOWIRES; SWITCHING DELAYS; SWITCHING RESPONSE; TRANSVERSE COMPONENTS;

CARRIER MOBILITY; ELECTRIC FIELDS; ELECTRIC POWER UTILIZATION; ELECTRIC WIRE; MOSFET DEVICES; NANOWIRES; SEMICONDUCTING SILICON COMPOUNDS;

DESIGN;

NANOMATERIAL; NANOWIRE; SILICON;

ARTICLE; ELECTRIC FIELD; ELECTRIC POTENTIAL; ELECTRONICS; ENERGY CONSUMPTION; INVERTER; NANOANALYSIS; NANODEVICE; NANOTECHNOLOGY; SEMICONDUCTOR; SIMULATION;

EID: 63349098175     PISSN: None     EISSN: 17500443     Source Type: Journal    
DOI: 10.1049/mnl:20080046     Document Type: Article

References (12)

1. Cui, Y., and Lieber, C.S.: ' Functional nanoscale electronic devices assembled using silicon nanowire building blocks ', Science, 2001, 291, p. 851-853 10.1126/science.291.5505.851 0036-8075
2. Cui, Y., Duan, X., Hu, J., and Lieber, C.S.: ' Doping and electrical transport in silicon nanowires ', J. Phys. Chem., 2000, 104, (22), p. 5213-5216 0022-3654
3. Sharma, A.K., Zaidi, S.H., Lucero, S., Brueck, S.R.J., and Islam, N.E.: ' Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs ', IEE Proc., Circuits Devices Syst., 2004, 151, (5), p. 422-430 1350-2409
4. Roy, A.S., Enz, C.C., and Sallese, J.M.: ' Compact modeling of gate sidewall capacitance of DG-MOSFET ', IEEE Trans. Electron Devices, 2006, 53, (10), p. 2655-2657 0018-9383
5. Cristoloveanu, S.: ' Silicon on insulator technologies and devices: From present to future ', Solid-State Electron., 2001, 45, (8), p. 1403-1411 10.1016/S0038-1101(00)00271-9 0038-1101
6. Jiménez, D., Sáenz, J.J., Iñíguez, B., Suñé, J., Marsal, L.F., and Pallarès, J.: ' Modeling of nanoscale gate-all-around MOSFETs ', IEEE Electron Device Lett., 2004, 25, p. 314-316 10.1109/LED.2004.826526 0741-3106
7. Jiménez, D., Iñíguez, B., Suñé, J., Marshal, L.F., and Pallarès, J.: ' Continuous analytic I-V model for surrounding-gate MOSFETs ', IEEE Electron Device Lett., 2004, 25, (8), p. 571-573 10.1109/LED.2004.831902 0741-3106
8. Fang, F.F., and Fowler, A.B.: ' Electron scattering in inverted silicon surfaces ', Phys. Rev. B, 1968, 169, (3), p. 619-631
9. Lombardi, C., Manzini, S., Saporito, A., and Vanzi, M.: ' A physically based mobility model for numerical simulation of nonplanar devices ', IEEE Trans. Comput.-Aided Des., 1988, 7, p. 1164-1171 0278-0070
10. Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, S., and Yamada, J.: ' 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS ', IEEE J. Solid-State Circuits, 1995, 30, (8), p. 847-854 10.1109/4.400426 0018-9200
11. Buddharaju, K.D., Singh, N., and Rustagi, H.C.: et al. ' Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach ', Solid-State Electron., 2008, 52, (9), p. 1312-1317 10.1016/j.sse.2008.04.017 0038-1101
12. ' Device Simulation Software ', (Silvaco International, California, USA, 2000)