Compact modeling of gate sidewall capacitance of DG-MOSFET

IEEE Transactions on Electron Devices

Volumn 53, Issue 10, 2006, Pages 2655-2657

  Roy, Ananda S ^a   Enz, Christian C ^a,b   Sallese, J M ^a  

^a EPFL   (Switzerland)

^b CSEM   (Switzerland)

Author keywords

Conformal mapping; Double gate MOSFET; Fringe capacitance; Gate underlap

Indexed keywords

ANALYTICAL MODELS; COMPACT MODELING; DESIGN AND OPTIMIZATIONS; DG-MOSFET; DOUBLE GATE MOSFET; DOUBLE-GATE DEVICES; FRINGE CAPACITANCE; GATE UNDERLAP; SEMI-EMPIRICAL TECHNIQUES;

CONFORMAL MAPPING; MOSFET DEVICES;

CAPACITANCE;

EID: 63349096863     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.882029     Document Type: Article

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