메뉴 건너뛰기




Volumn , Issue , 2008, Pages 227-233

Active control and digital rights management of integrated circuit IP cores

Author keywords

Active IP control; IP protection; Security

Indexed keywords

ACTIVE CONTROLS; ACTIVE IP CONTROL; BUSINESS MODELS; CONTROL METHODS; CONTROL STRUCTURES; DELAY OVERHEADS; DIGITAL RIGHTS MANAGEMENTS; INTELLECTUAL PROPERTY CORES; IP CORES; IP PROTECTION; LOW AREAS; LOW OVERHEADS; MANUFACTURING FLOWS; PARADIGM SHIFTS; SECURITY; TRUSTED THIRD PARTIES;

EID: 63349086739     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450095.1450129     Document Type: Conference Paper
Times cited : (37)

References (26)
  • 3
    • 84869268536 scopus 로고    scopus 로고
    • The international technology roadmap for semiconductors itrs
    • "The international technology roadmap for semiconductors (itrs)", http://www.itrs.net/.
  • 5
    • 85077688405 scopus 로고    scopus 로고
    • Active hardware metering for intellectual property protection and security
    • Y. Alkabani and F. Koushanfar. Active hardware metering for intellectual property protection and security. In USENIX Security Symposium, pages 291-306, 2007.
    • (2007) USENIX Security Symposium , pp. 291-306
    • Alkabani, Y.1    Koushanfar, F.2
  • 8
    • 51549088218 scopus 로고    scopus 로고
    • Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability
    • Y. Alkabani, T. Massey, F. Koushanfar, and M. Potkonjak. Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability. In Design Automation Conference (DAC), 2008.
    • (2008) Design Automation Conference (DAC)
    • Alkabani, Y.1    Massey, T.2    Koushanfar, F.3    Potkonjak, M.4
  • 15
    • 4544381402 scopus 로고    scopus 로고
    • A technique to build a secret key in integrated circuits for identification and authentication applications
    • J. Lee, L. Daihyun, B. Gassend, G. Suh, M. van Dijk, and S. Devadas. A technique to build a secret key in integrated circuits for identification and authentication applications. In Symposium of VLSI Circuits, pages 176-179, 2004.
    • (2004) Symposium of VLSI Circuits , pp. 176-179
    • Lee, J.1    Daihyun, L.2    Gassend, B.3    Suh, G.4    van Dijk, M.5    Devadas, S.6
  • 18
    • 67249147207 scopus 로고    scopus 로고
    • M. Majzoobi, F. Koushanfar, and M. Potkonjak. Testing techniques for hardware security. In ITC, 2008.
    • M. Majzoobi, F. Koushanfar, and M. Potkonjak. Testing techniques for hardware security. In ITC, 2008.
  • 19
    • 85014926558 scopus 로고    scopus 로고
    • A security tagging scheme for asic designs and intellectual property cores
    • January
    • C. Marsh and T. Kean. A security tagging scheme for asic designs and intellectual property cores. Design & Reuse, January 2007.
    • (2007) Design & Reuse
    • Marsh, C.1    Kean, T.2
  • 20
    • 0035440030 scopus 로고    scopus 로고
    • Techniques for the creation of digital watermarks in sequential circuit designs
    • A. Oliveira. Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Trans. CAD of Integrated Circuits and Systems, 20(9):1101-1117, 2001.
    • (2001) IEEE Trans. CAD of Integrated Circuits and Systems , vol.20 , Issue.9 , pp. 1101-1117
    • Oliveira, A.1
  • 26
    • 33845577055 scopus 로고    scopus 로고
    • Information hiding in finite state machine
    • L. Yuan and G. Qu. Information hiding in finite state machine. In Information Hiding Workshop, pages 340-354, 2004.
    • (2004) Information Hiding Workshop , pp. 340-354
    • Yuan, L.1    Qu, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.