FPGA implementation of an image recognition system based on tiny neural networks and on-line reconfiguration

IECON Proceedings (Industrial Electronics Conference)

Volumn , Issue , 2008, Pages 2445-2452

  Moreno, Félix ^a   Alarcón, Jaime ^a   Salvador, Rubén ^a   Riesgo, Teresa ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC MODELS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE RECOGNITION; INDUSTRIAL ELECTRONICS;

APPLICATION-SPECIFIC DEMANDS; BACK-PROPAGATION LEARNING; DYNAMIC RECONFIGURATIONS; EXPANDABILITY; FPGA IMPLEMENTATIONS; HARDWARE ARCHITECTURES; IMAGE RECOGNITION SYSTEMS; LEARNING ABILITIES; PERCEPTRON NETWORKS; PERFORMANCE BENEFITS; PROCESSING STEPS; ROBOT CONTROLS; RUN-TIME; SECURITY APPLICATIONS; SIMULATION RESULTS; SYSTEM ARCHITECTURES; WEIGHT MODIFICATIONS;

NEURAL NETWORKS;

EID: 63149087253     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IECON.2008.4758340     Document Type: Conference Paper

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