The totem neurochip: An FPGA implementation

Proceedings of the Fourth IEEE International Symposium on Signal Processing and Information Technology, ISSPIT 2004

Volumn , Issue , 2004, Pages 461-464

  Avogadro, M ^a   Bera, M ^a   Danese, G ^a   Leporati, F ^a   Spelgatti, A ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

Multiprocessing; Neural Networks; Real Time systems; Reconfigurable architectures

Indexed keywords

ARITHMETIC UNITS; NEUROCHIPS; REACTIVE TABU SEARCH ALGORITHM; RECONFIGURABLE ARCHITECTIRES;

COMPUTER SIMULATION; LEARNING ALGORITHMS; MONTE CARLO METHODS; MULTIPROCESSING SYSTEMS; NEURAL NETWORKS; RANDOM ACCESS STORAGE; REAL TIME SYSTEMS; TABLE LOOKUP;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 21544455815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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