FPGA implementation of a multilayer perceptron neural network using VHDL

International Conference on Signal Processing Proceedings, ICSP

Volumn 2, Issue , 1998, Pages 1311-1314

  Taright, Yamina ^a   Hubin, Michel ^a  

^a UNIVERSITÉ ET INSA DE ROUEN   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SYSTEMS PROGRAMMING; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SENSOR DATA FUSION;

STATIC RANDOM ACCESS MEMORY (SRAM);

MULTILAYER NEURAL NETWORKS;

EID: 0032265783     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (6)