A full current-mode sense amplifier for low-power SRAM applications

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 1402-1405

  Do, Anh Tuan ^a   Shern, Jeremy Low Yung ^a   Kong, Zhi Hui ^a   Yeo, Kiat Seng ^a   Lih, Joshua Low Yung ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CHARTERED SEMICONDUCTOR MANUFACTURING; CMOS TECHNOLOGIES; CROSS-COUPLED; CURRENT-MODE SENSE AMPLIFIERS; GLOBAL SENSING; HIGH-SPEED; LOW-POWER; LOW-POWER SRAM; NEW DESIGNS; POWER CONSUMPTION; SIMULATION RESULTS; SUPPLY VOLTAGES; ULTRA-HIGH SPEED;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; SIMULATED ANNEALING;

STATIC RANDOM ACCESS STORAGE;

EID: 62949176281     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746292     Document Type: Conference Paper

References (17)

1. B. D. Yang, and L. S. Kim, "A low-power SRAM using hierarchical bit line and local sense amplifier", IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1366-1376, Jun. 2005.
2. 2002 International Technology Roadmap for Semiconductors.
3. M. Margala, "Low-power SRAM circuit design," in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 115-122, 1999.
4. B. S. Amrutur, and M. A. Horowitz, "A replica technique for wordline and sense control in low-power SRAM's," IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1208-1219, Aug. 1998.
5. E. A. Ramy, and A. B. Magdy, "Low-power cache design using 7T SRAM cell," IEEE Trans. Circuits and System-II Express Briefs, vol. 54, no. 4, pp. 318-322, Apr. 2007.
6. J. L. Shin, B. Petrick, M. Singh, and A. Leon, "Design and implementation of an embedded 512-KB level-2 cache subsystem," IEEE J. Solid-State Circuit, vol. 40, no. 9, pp. 1815-1820, Sep. 2005.
7. E. Seevinck, P. J. V. Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current SA for CMOS SRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 5, pp. 525-536, May 1991.
8. S. Katsuro, I. Koichiro, U. Kiyotsugu, K. Kunihiro, H. Naotaka, T. Hiroshi, K. Fumio, Y. Toshiaki, and S. Akihiro, "A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier," IEEE J. Solid-State Circuits, vol. 21, no. 11, pp. 1511-1518, Nov. 1992.
9. K. S. Yeo, "New current conveyor for high-speed low-power current sensing," IEE Proc. Circuits Dev. Syst., vol. 145, no. 2, pp. 85-89, Apr. 1998.
10. A. Hajimiri, and R. Heald, "Design issues in cross-coupled inverter sense amplifier," in IEEE Int. Symp. Circuits and Systems, vol. 2, pp. 149-152, 1998.
11. K. S. Yeo, W. L. Goh, Z. H. Kong, Q. X. Zhang, and W. G. Yeo, "High-performance, low-power current sense amplifier using a cross-coupled current-mirror configuration," IEE Proc. Circuits Dev. Syst., vol. 149, no. 5-6, pp. 308-314, Oct./Dec. 2002.
12. R. Singh, and N. Bhat, "An offset compensation technique for latch type sense amplifier in high-speed low-power SRAMs," IEEE Trans. Very Large Scale Integration (VLSI) System, vol. 12, no. 6, pp. 652-657, Jun. 2004.
13. H. C. Chow, and S. H. Chang, "High performance sense amplifier circuit for low power SRAM applications," in IEEE Int. Symp. Circuits and Systems, vol 2, part 2, pp. 741-744, 2004.
14. Z. H. Kong, K. S. Yeo, and C. H. Chang, "An ultra low-power current-mode sense amplifier for SRAM applications," J. Circuits, Systems & Computers, vol. 14, no. 5, pp. 939-951, 2005.
15. C. L. Hsu, M. H. Ho, and C. F. Lin, "New current-mirror sense amplifier design for high speed SRAM applications," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E.89-A, pp. 377-384, 2006.
16. Z. H. Kong, A. T. Do, and K. S. Yeo, "Design of a current sense amplifier using a current distribution technique," in Int. Ph.D Student Workshop on SoC, pp. 41-43, Jul. 2007.
17. S. Patil, M. Wieckowski, and M. Margala, "A self-biased charge-transfer sense amplifier," in IEEE Int. Symp. Circuits and Syst., vol. 4, pp. 3030-3033, 2007.