A memory efficient partially parallel decoder architecture for QC-LDPC codes

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 2005, Issue , 2005, Pages 729-733

  Wang, Zhongfeng ^a   Cui, Zhiqiang ^a  

^a Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DECODING; PARALLEL PROCESSING SYSTEMS;

CHECK NODE PROCESSING; COMPUTATION DELAY; LOW DENSITY PARITY CHECK CODES; MIN SUM DECODING ALGORITHM;

CODES (SYMBOLS);

EID: 33847644172     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. R. G. Gallager, "Low-density parity-check codes," IRE Transactions on Information Theory, vol. IT-8, pp. 21-28, Jan. 1962.
2. M. P. C. Fossorier, "Quasi-cyclic low-density parity-check codes from circulant permutation matrices," IEEE Trans. on Info. Theory, vol. 50, pp. 1788 - 1793, Aug. 2004.
3. Z. Li and B. V. K. V. Kumar, "A class of good quasi-cyclic low-density parity check codes based on progressive edge growth graph," Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 1990-1994, 2004.
4. L. Chen, J. Xu, I. Djurdjevic and S. Lin, "Near-Shannon-Limit Quasi-Cyclic Low-Density Parity-Check Codes," IEEE Transactions on Communications, vol. 52, pp. 1038-1042, Jul. 2004.
5. "LDPC coding for OFDMA PHY," http:/www.ieee802.org/16/tge/
6. J. Chen and M. Fossorier, "Near optimum universal belief propagation based decoding of low-density parity check codes," IEEE Trans. Commun., vol. 50, pp. 406-414, Mar. 2002.
7. M. Cocco, J. Dielissen, M. Heijligers, A. Hekstra, J. Huisken, "A scalable architecture for LDPC decoding," Automation and Test in Europe Conference and Exhibition, vol. 3, pp. 88-93, Feb. 2004.
8. T. Zhang and K. K. Parhi, "Joint (3, k)-Regular LDPC Code and Decoder/Encoder Design," IEEE Transactions on Signal Processing, vol. 52, pp. 1065-1079, Apr. 2004.
9. Z. Wang, Y. Chen and K. Parhi, "Area-efficient quasi-cyclic LDPC code decoder architecture," in proc. of ICASSP 2004, vol. 5, pp. 49-52, May 2004.
10. Z. Wang and Q. Jia, "Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes," in proc. of IEEE ISCAS'05, May 2005.
11. Y. Chen and D. Hocevar, "A FPGA and ASIC implementation of rate-1/2, 8088-b irregular low density parity check decoder," IEEE GLOBECOM'03, vol. 1, pp. 113-117, Dec. 2003.