Optical lithography technologies for 45nm-node CMOS

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5754, Issue PART 1, 2005, Pages 196-203

  Mimotogi, Shoji ^a   Uesawa, Fumikatsu ^b   Kyoh, Suigen ^a   Fujise, Hiroharu ^a   Shiobara, Eishi ^a   Katsumata, Mikio ^b   Hane, Hiroki ^b   Sugiyama, Tomohiro ^b   Sho, Koutaro ^a   Miyazaki, Maki ^a   Takahata, Kazuhiro ^a   Kanai, Hideki ^a   Sato, Kazuya ^a   Hashimoto, Kohji ^a  

^a TOSHIBA CORPORATION   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

Alt. PSM; High density SRAM; Immersion lithography; MEF; Robust design

Indexed keywords

ABERRATIONS; CMOS INTEGRATED CIRCUITS; MASKS; ROBUSTNESS (CONTROL SYSTEMS); SENSITIVITY ANALYSIS; STATIC RANDOM ACCESS STORAGE;

ALT. PSM; HIGH DENSITY SRAM; IMMERSION LITHOGRAPHY; MEF; ROBUST DESIGN;

PHOTOLITHOGRAPHY;

EID: 25144472061     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.600948     Document Type: Conference Paper

References (2)

1. Kohji Hashimoto et al., "ArF Lithography Technologies for 65nm-node CMOS (CMOS5) with 30nm Logic Gate and High Density Embedded Memories", Proc. of VLSI symposium 2003, 4B-2
2. F. Uesawa et al., "Lithography of choice for the 45-nm node: new medium, new wavelength, or new beam?", SPIE Vol. 5377, 34(2004)