A model for electric degradation of interconnect low- k dielectrics in microelectronic integrated circuits

Journal of Applied Physics

Volumn 105, Issue 4, 2009, Pages

  Haase, Gaddi S ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; APPROXIMATION THEORY; CHARGE COUPLED DEVICES; DEGRADATION; DIELECTRIC MATERIALS; ELECTRIC FIELDS; INTEGRATED CIRCUITS; METALLIC COMPOUNDS; MOS DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR MATERIALS;

ACCELERATED TESTS; COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TECHNOLOGIES; CONSTANT VOLTAGE STRESS; DEGRADATION MODELS; DEGRADATION PROCESS; E MODELS; ELECTRIC DEGRADATIONS; FUTURE TECHNOLOGIES; GATE OXIDES; HIGH VOLTAGES; INDUCED DEGRADATIONS; INTERCONNECT SYSTEMS; LOW-K DIELECTRICS; METAL LINES; MICRO-ELECTRONIC DEVICES; OPERATING CONDITIONS; OPERATING VOLTAGES; RELIABILITY ENGINEERINGS; SCALING DOWNS; SIMPLE MODELS; TIME BEHAVIORS; TRAPPED CHARGES;

METAL REFINING;

EID: 61449257455     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3073989     Document Type: Article

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