An abstraction-based decision procedure for bit-vector arithmetic

International Journal on Software Tools for Technology Transfer

Volumn 11, Issue 2, 2009, Pages 95-104

  Bryant, Randal E ^a   Kroening, Daniel ^b   Ouaknine, Joël ^b   Seshia, Sanjit A ^c   Strichman, Ofer ^d   Brady, Bryan ^c  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b UNIVERSITY OF OXFORD   (United Kingdom)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Bit vector; Decision procedures

Indexed keywords

ABSTRACTING; BOOLEAN FUNCTIONS; MODEL CHECKING;

BOOLEAN VARIABLES; BOUNDED MODELS; DATA TYPES; DECISION-PROCEDURES; ESSENTIAL COMPONENTS; PROPOSITIONAL LOGIC; SAT SOLVERS; SATISFYING ASSIGNMENTS; UNDER APPROXIMATIONS; UNSATISFIABLE CORES; VECTOR OPERATIONS;

VECTORS;

EID: 60849104065     PISSN: 14332779     EISSN: 14332787     Source Type: Journal    
DOI: 10.1007/s10009-009-0101-x     Document Type: Article

References (29)

1. Arons, T., Elster, E., Fix, L., Mador-Haim, S., Mishaeli, M., Shalev, J., Singerman, E., Tiemeyer, A., Vardi, M.Y., Zuck, L.D.: Formal verification of backward compatibility of microcode. In: Proceedings of the Computer-Aided Verification (CAV'05). LNCS, vol. 2404, pp. 185-198 (2005)
2. Babic, D., Spear, F.H.: Proceedings of the SAT 2007 competition (2007)
3. Babić, D., Musuvathi, M.: Modular Arithmetic Decision Procedure. Technical report, Microsoft Research, Redmond (2005)
4. Barrett, C.W., Dill, D.L., Levitt, J.R.: A decision procedure for bit-vector arithmetic. In: Proceedings of DAC'98, pp. 522-527. ACM Press, New York (1998)
5. Biere, A., Cimatti, A., Clarke, E., Yhu, Y.: Symbolic model checking without BDDs. In: TACAS, pp. 193-207 (1999)
6. Brinkmann, R., Drechsler, R.: RTL-datapath verification using integer linear programming. In: Proceedings of VLSI Design, pp. 741-746. IEEE (2002)
7. Bryant, R.E.: Term-Level Verification of a Pipelined CISC Microprocessor. Technical Report CMU-CS-05-195, Computer Science Department, Carnegie Mellon University (2005)
8. Bryant, R.E., Kroening, D., Ouaknine, J., Seshia, S.A., Strichman, O., Brady, B.A.: Deciding bit-vector arithmetic with abstraction. In: Grumberg, O., Huth, M. (eds.) 13th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS'07), pp. 358-372 (2007)
9. Cadar, C., Ganesh, V., Pawlowski, P.M., Dill, D.L., Engler, D.R.: EXE: automatically generating inputs of death. In: 13th ACM Conference on Computer and Communications Security (CCS '06), pp. 322-335. ACM, New York (2006)
10. Clarke, E., Kroening, D.: Hardware verification using ANSI-C programs as a reference. In: Proceedings of ASP-DAC 2003, pp. 308-311. IEEE Computer Society Press, Washington (2003)
11. CoAk, B., Kroening, D., Sharygina, N.: Cogent: accurate theorem proving for program verification. In: Proceedings of CAV 2005, pp. 296-300. Springer, Berlin (2005)
12. Cyrluk, D., Möller, M.O., Rueß, H.: An efficient decision procedure for the theory of fixed-sized bit-vectors. In: Computer-Aided Verification (CAV '97), pp. 60-71 (1997)
13. Dutertre, B., de Moura, L.: The Yices SMT solver. Available at http:// yices.csl.sri.com/tool-paper.pdf (2006)
14. Ganesh, V., Berezin, S., Dill, D.: A decision procedure for fixed-width bit-vectors. Technical Report, Computer Science Department, Stanford University (2005)
15. Ganesh, V., Dill, D.L.: A decision procedure for bit-vectors and arrays. In: Computer Aided Verification (CAV '07), Berlin, Germany, July 2007. Springer, Berlin (2007)
16. Gupta, A., Ganai, M., Yang, Z., Ashar, P.: Iterative abstraction using SAT-based BMC with proof analysis. In: ICCAD (2003)
17. Huang, C.-Y., Cheng, K.-T.: Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. In: Proceedings of DAC, pp. 118-123 (2000)
18. Kroening, D., Ouaknine, J., Seshia, S., Strichman, O.: Abstraction-based satisfiability solving of Presburger arithmetic. In: Alur R., Peled D. (eds.) Proceedings of the 16th International Conference on Computer Aided Verification (CAV'04). LNCS, vol. 3114, pp. 308-320, Boston, MA, July 2004. Springer, Berlin (2004)
19. Lahiri, S., Mehra, K.: Interpolant Based Decision Procedure for Quantifier-Free Presburger Arithmetic. Technical Report 2005-121, Microsoft Research (2005)
20. McMillan, K., Amla, N.: Automatic abstraction without counterexamples. In: Garavel, H., Hatcliff, J. (eds.) TACAS'03. Lect. Notes in Comp. Sci., vol. 2619 (2003)
21. MiniSat. http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat/
22. Moscow, M.L.: http://www.dina.dk/~sestoft/mosml.html
23. Parthasarathy, G., Iyer, M.K., Cheng, K.-T., Wang, L.-C.: An efficient finite-domain constraint solver for circuits. In: Design Automation Conference (DAC), pp. 212-217 (2004)
24. Tseitin, G.: On the complexity of proofs in poropositional logics. In: Siekmann, J., Wrightson, G. (eds.) Automation of Reasoning: Classical Papers in Computational Logic 1967-1970, volume 2. Springer-Verlag, 1983. Originally published 1970
25. UCLID verification system. http://www.cs.cmu.edu/~uclid
26. Wedler, M., Stoffel, D., Kunz, W.: Normalization at the arithmetic bit level. In: Proceedings of DAC, pp. 457-462. ACM Press, New York (2005)
27. Wisconsin Safety Analyzer Project. http://www.cs.wisc.edu/wisa
28. Xie, Y., Aiken, A.: Scalable error detection using Boolean satisfiability. In: Proceedings of the 32nd ACM Symposium on Principles of Programming Languages (POPL), pp. 351-363 (2005)
29. Zhang, L., Malik, S.: Extracting small unsatisfiable cores from unsatisfiable boolean formulas. In: In Sixth International Conference on Theory and Applications of Satisfiability Testing (SAT2003), S. Margherita Ligure (2003)