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Volumn , Issue , 2000, Pages 118-123
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Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques
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Author keywords
[No Author keywords available]
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Indexed keywords
ALGORITHMS;
BOOLEAN ALGEBRA;
CONSTRAINT THEORY;
CRITICAL PATH ANALYSIS;
DECISION MAKING;
LOGIC CIRCUITS;
LOGIC DESIGN;
LOGIC GATES;
ASSERTION CHECKING;
BIT VECTOR VALUE MODULATION;
FALSE NEGATIVE EFFECT;
MODULAR ARITHMETIC CONSTRAINT SOLVING TECHNIQUES;
RESISTOR TRANSISTOR LOGIC;
TARGET ASSERTION PROPERTY;
WORD LEVEL AUTOMATIC TEST PATTERN GENERATION;
PROGRAM DIAGNOSTICS;
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EID: 0033714214
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/337292.337333 Document Type: Conference Paper |
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Times cited : (35)
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References (18)
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