An efficient finite-domain constraint solver for circuits

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 212-217

  Parthasarathy, G ^a   Iyer, M K ^a   Cheng, K T ^a   Wang, Li C ^a  

^a University of California   (United States)

Author keywords

Bit vector arithmetic; Boolean Satisfiability; Decision Procedures; Design Verification; Integer Linear Programming

Indexed keywords

ALGEBRA; FORMAL LOGIC; INTEGER PROGRAMMING; LINEAR PROGRAMMING; PROBLEM SOLVING; THEOREM PROVING; VECTORS;

BIT-VECTOR ARITHMETIC; BOOLEAN SATISFIABILITY; DECISION PROCEDURES; DESIGN VERIFICATION;

INTEGRATED CIRCUITS;

EID: 4444237823     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996628     Document Type: Conference Paper

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