Formal verification of backward compatibility of microcode

Lecture Notes in Computer Science

Volumn 3576, Issue , 2005, Pages 185-198

  Arons, Tamarah ^a   Elster, Elad ^a   Fix, Limor ^a   Mador Haim, Sela ^b   Mishaeli, Michael ^a   Shalev, Jonathan ^a   Singerman, Eli ^a   Tiemeyer, Andreas ^a   Vardi, Moshe Y ^c   Zuck, Lenore D ^d  

^a INTEL CORPORATION   (United States)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^c RICE UNIVERSITY   (United States)

^d UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; ENCODING (SYMBOLS); PROCESSING;

FORMAL VERIFICATION; MICROCODES;

COMPUTER SOFTWARE;

EID: 26444563295     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11513988_20     Document Type: Conference Paper

References (17)

1. [AHKV98] R. Alur, T.A. Henzinger, O. Kupferman, and M.Y. Vardi. Alternating refinement relations. In CONCUR'98:163-178, 1998.
2. [BR02] T. Ball and S.K. Rajamani. The SLAM project: debugging system software via static analysis. In POPL'02:1-3, 2002.
3. [CHRF00] D.W. Currie, A.J. Hu, S. Rajan, and M. Fujita. Automatic formal verification of DSP software. In DAC'00: 130-135, 2000.
4. [CKY03] E.M. Clarke, D. Kroening, and K. Yorav. Behavioral consistency of C and Verilog programs using bounded model checking. In DAC'03: 368-371, 2003.
5. [Cyr93] D. Cyrluk. Microprocessor Verification in PVS: A Methodology and Simple Example. Technical Report SRI-CSL-93-12, Menlo Park, CA, 1993.
6. [FH02] X. Feng and A.J. Hu. Automatic formal verification for scheduled VLIW code. In ACM SIGPLAN Joint Conference: Languages, Compilers, and Tools for Embedded Systems, and Software and Compilers for Embedded Systems, pages 85-92, 2002.
7. [HC98] S.Y. Huang and K.T. Cheng. Formal Equivalence Checking and Design Debugging. Kluwer, 1998.
8. [HJMS03] T.A. Henzinger, R. Jhala, R. Majumdar, and G. Sutre. Software verification with Blast. In SPIN'03:235-239, 2003.
9. [HP85] D. Harel and A. Pnueli. On the development of reactive systems. In Logics and Models of Concurrent Systems, volume F-13 of NATO ASI Series, pages 477-498, 1985.
10. [HUK00] K. Hamaguchi, H. Urushihara, and T. Kashiwabara. Symbolic checking of signal-transition consistency for verifying high-level designs. In FMCAD'00:445-469, 2000.
11. [MP95] Z. Manna and A. Pnueli. Temporal Verification of Reactive Systems: Safety. Springer-Verlag, New York, 1995.
12. [Nec00] G. Necula. Translation validation of an optimizing compiler. In PLDI'00: 83-94, 2000.
13. [PSS98] A. Pnueli, M. Siegel, and E. Singerman. Translation validation. In TACAS'98:151-161, 1998.
14. [SH02] J. Sawada and W.A. Hunt. Verification of FM9801: An out-of-order microprocessor model with speculative execution, exceptions, and program-modifying capability. J. on Formal Methods in System Design, 20(2): 187-222, 2002.
15. [SM96] M. Srivas and S. Miller. Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods. J. on Formal Methods in System Design, 8:153-188, 1996.
16. [Sta02] W. Stallings. Computer Organization and Architecture, 6th ed. Prentice Hall, 2002.
17. [ZPFG03] L. Zuck, A. Pnueli, Y. Fang, and B. Goldberg. Voc: A translation validator for optimizing compilers. J. of Universal Computer Science, 9(2), 2003.