Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation

Journal of Zhejiang University: Science A

Volumn 10, Issue 2, 2009, Pages 151-164

  Huang, Kai ^a   Yan, Xiao Lang ^a   Han, Sang Il ^b   Chae, Soo Ik ^b   Jerraya, Ahmed A ^c   Popovici, Katalin ^d   Guerin, Xavier ^d   Brisolara, Lisane ^e   Carro, Luigi ^e  

^a ZHEJIANG UNIVERSITY   (China)

^b Seoul National University   (South Korea)

^c CEA LETI   (France)

^d TIMA LABORATORY   (France)

^e FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

H.264; Motion JPEG; Multiprocessor system on chip (MPSoC) design; Refinement; Simulink; SystemC

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPLICATIONS; COMPUTER ARCHITECTURE; DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; LOGIC DESIGN; PROGRAMMABLE LOGIC CONTROLLERS; SPACE RESEARCH; SYSTEMS ANALYSIS;

H.264; MOTION-JPEG; MULTIPROCESSOR SYSTEM-ON-CHIP (MPSOC) DESIGN; REFINEMENT; SIMULINK; SYSTEMC;

MULTIPROCESSING SYSTEMS;

EID: 60349090336     PISSN: 1673565X     EISSN: 18621775     Source Type: Journal    
DOI: 10.1631/jzus.A0820085     Document Type: Article

References (20)

1. F. Balarin Y. Watanabe H. Hsieh L. Lavagno C. Passerone A. Sangiovanni-Vincentelli 2003 Metropolis: an integrated electronic system design environment IEEE Computer 36 4 45 52
2. Bouchhima, A., Chen, X., Frédéric, P., Wander, C., Jerraya, A., 2005. A Unified HW/SW Interface Model to Remove Discontinuities Between HW and SW Design. Proc. EMSOFT, p.18-22. [doi:10.1145/1146909.1146981]
3. W.O. Cesario G. Nicolescu L. Gauthier D. Lyonnard A.A. Jerraya 2001 Colif: a design representation for application-specific multiprocessor SoC IEEE Design Test Comput. 18 5 18 20
4. W.O. Cesario D. Lyonnard G. Nicolescu Y. Paviot S.J. Yoo A.A. Jerraya L. Gauthier M. Diaz-Nava 2002 Multiprocessor SoC platforms: a component-based design approach IEEE Des. Test Comput. 19 6 52 63
5. Gajski, D.D., Zhu, J.W., Dömer, R., Gerstlauer, A., Zhao, S.Q., 2000. SpecC: Specification Language and Methodology. Kluwer Academic Publishers, Boston.
6. Grant, M., 2006. Overview of the MPSoC Design Challenge. Proc. Design Automation Conf., p.274-279. [doi:10.1145/1146909.1146980]
7. Han, S.I., Baghdadi, A., Bonaciu, M., Chae, S.I., Jerraya, A.A., 2004. An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory. Proc. Design Automation Conf., p.250-255. [doi:10.1145/996566.996636]
8. Han, S.I., Chae, S.I., Jerraya, A.A., 2006a. Functional Modeling Techniques for Efficient SW Code Generation of Video Codec Applications. Proc. Conf. on Asia South Pacific Design Automation, p.935-940. [doi:10.1145/1118299. 1118509]
9. Han, S.I., Guerin, X., Chae, S.I., Jerraya, A.A., 2006b. Buffer Memory Optimization for Video Codec Application Modeled in Simulink. Proc. Design Automation Conf., p.689-694. [doi:10.1145/1146909.1147084]
10. Huang, K., Han, S.I., Popovici, K., Brisolara, L., Guerin, X., Li, L., Yan, X.L., Chae, S.I., Carro, L., Jerraya, A.A., 2007. Simulink-based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. Proc. Design Automation Conf., p.39-42. [doi:10.1145/1278480.1278491]
11. A.A. Jerraya W. Wolf 2005 Hardware/Software interface co-design for embedded systems IEEE Computer 38 2 63 69
12. A.A. Jerraya H. Tenhunen W. Wolf 2005 Guest editors' introduction: multiprocessor systems-on-chips Computer 38 7 36 40
13. Jerraya, A.A., Bouchhima, A., Petrot, F., 2006. Programming Models and HW-SW Interfaces Abstraction for Multi-Processor SoC. Proc. Design Automation Conf., p.280-285. [doi:10.1145/1146909.1146981]
14. Kahn, G., MacQueen, D.B., 1977. Coroutines and Networks of Parallel Processes. Proc. Information Processing, Toronto, Canada, p.993-998.
15. T. Kangas P. Kukkala H. Orsila E. Salminen M. Hannikainen T.D. Hammalainen J. Rihimaki K. Kuusilinna 2006 UML-based multiprocessor SoC design framework ACM Trans. Embed. Comput. Syst. 5 2 281 320
16. K. Keutzer A.R. Newton J.M. Rabaey A. Sangiovanni-Vincentelli 2000 System-level design: orthogonalization of concerns and platform-based design IEEE Trans. CAD Integr. Circuits Syst. 19 12 1523 1543
17. J. Ou V.K. Prasanna 2005 Design space exploration using arithmetic level hardware-software co-simulation for configurable multi-processor platforms ACM Trans. Embed. Comput. Syst. 2 3 111 137
18. A.D. Pimentel L.O. Hertzbetger P. Lieverse P. van der Wolf E.E. Deprettere 2001 Exploring embedded-systems architectures with Artemis IEEE Computer 34 11 57 63
19. Reynari, L.M., Cucinotta, F., Serra, A., Lavagno, L., 2001. A Hardware/Software Co-design Flow and IP Library Based on SimulinkTM. Proc. Design Automation Conf., p.593-598.
20. X.L. Yan L.L. Yu J.B. Wang 2004 A front-end automation tool supporting design, verification and reuse of SoC J. Zhejiang Univ. Sci. 5 9 1102 1105