Front-end automation tool supporting design, verification and reuse of SOC

Journal of Zhejiang University: Science

Volumn 5, Issue 9, 2004, Pages 1102-1105

  Yan, Xiao Lang ^a   Yu, Long Li ^a   Wang, Jie Bing ^b  

^a ZHEJIANG UNIVERSITY   (China)

^b C Sky Microsystems   (China)

Author keywords

HDL; Reuse; System on Chip; Verification; Verilog

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; C (PROGRAMMING LANGUAGE); DATA PROCESSING; DATABASE SYSTEMS;

SYSTEM-ON-CHIP; VERIFICATION; VERILOG CODE; VPER1;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

ALGORITHM; ARTICLE; COMPUTER AIDED DESIGN; COMPUTER INTERFACE; COMPUTER LANGUAGE; COMPUTER PROGRAM; EQUIPMENT; EQUIPMENT DESIGN; METHODOLOGY; MICROCOMPUTER;

ALGORITHMS; COMPUTER-AIDED DESIGN; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; MICROCOMPUTERS; PROGRAMMING LANGUAGES; SOFTWARE; SOFTWARE DESIGN; USER-COMPUTER INTERFACE;

EID: 10944256348     PISSN: 10093095     EISSN: None     Source Type: Journal    
DOI: 10.1631/jzus.2004.1102     Document Type: Article

References (7)

1. Bening, L., Hornung, B., Pflederer, R., 2001. Hardware Description Language-Embedded Regular Expression Support for Module Iteration and Interconnection. Proc. International Hardware Description Language Conference.
2. Bening, L., Foster, H., 2001. Principles of Verifiable RTL Design, Second Edition. Kluwer Academics, USA, p.31-37.
3. Cummings, C.E., 2001. Verilog-2001 Behavioral and Synthesis Enhancements. HDLCON2001, Revl.3.
4. Davis, B., Mudge, T., 1995. A Verilog Preprocessor for Representing Datapath Components. Proceedings of the 4th International Verilog Conference, p.90-98.
5. IEEE Std 1364, 1995. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.
6. IEEE Std 1364, 2001. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.
7. Keating, M., Bricaud, P., 2002. Reuse Methodology Manual, 3rd edition. Kluwer Academics.