Statistical timing models for large macro cells and IP blocks considering process variations

IEEE Transactions on Semiconductor Manufacturing

Volumn 22, Issue 1, 2009, Pages 3-11

  Goel, Amit ^a   Vrudhula Sr , Sarma ^b   Taraporevala, Feroze ^a   Ghanta, Praveen ^a  

^a SYNOPSYS INC   (United States)

^b Arizona State University   (United States)

Author keywords

Integrated circuit timing; Macro cells; Process variations; Semiconductor process modeling

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIES; ELECTRIC CONDUCTIVITY; INTEGRATED CIRCUITS; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; SEMICONDUCTOR MATERIALS; TIME MEASUREMENT;

DESIGN BLOCKS; HIGH-PERFORMANCE SYSTEMS; INDUSTRIAL DESIGNS; INTEGRATED CIRCUIT TIMING; INTERCONNECT PARAMETERS; IP BLOCKS; MACRO CELLS; NOVEL TECHNIQUES; PROCESS PARAMETERS; PROCESS VARIATIONS; SEMICONDUCTOR PROCESS MODELING; SPATIAL CORRELATIONS; STATISTICAL TIMING ANALYSIS; STATISTICAL TIMINGS; SUBNANOMETER; TIMING MODELS;

TIMING CIRCUITS;

EID: 59849124094     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2008.2011629     Document Type: Conference Paper

References (12)

1. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," in Proc. ASPDAC, 2003, pp. 271-276.
2. S. Bhardwaj, P. Ghanta, and S. Vrudhula, "A framework for statistical timing analysis using non-linear delay and slew models," in Proc. ICCAD. 2006, pp. 225-230.
3. S. Bhardwaj, S. Vrudhula, P. Ghanta, and Y. Cao, "Modeling of intta-die process variations for accurate analysis and optimization of nano-scale circuits," in Proc. DAC, 2006, pp. 791-796.
4. H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single pert-like traversal," in Proc. ICCAD, 2003, pp. 621-625.
5. A. J. Daga, L. Mize, S. Sripada, C. Wolff, and Q. Wu, "Automated timing model generation," in Proc. DAC, 2002, pp. 146-151.
6. J. E. Gentle, Numerical Linear Algebra for Applications in Statistics., New York: Springer-Verlag, 1998.
7. D. C. Montgomery and G. C. Runger, Applied Statistics and Probability for Engineers., Hoboken, NJ: Wiley, 2006.
8. C. W. Moon, H. Kriplani, and K. P. Belkhale, "Timing model extraction of hierarchical blocks by graph reduction," in Proc. DAC, 2002, pp. 152-157.
9. K. Okada, K. Yamaoka, and H. Onodera, "A statistical gate delay model for intra-chip and inter-chip variabilities," in Proc. ASPDAC, 2003, pp. 31-36.
10. A. Papoulis and S. U. Pillai, Probability, Random Variables and Stochastic Processes., 3rd ed. New York: McGraw-Hill, 1991.
11. H. Yalcin, M. Mortazavi, R. Palermo, C. Bamji, and K. Sakallah, "Functional timing analysis for IP characterization," in Proc. DAC, 1999, pp. 731-736.
12. L. Zhang, Y. Hu, and C. C.-P. Chen, "Statistical timing analysis with path reconvergence and spatial correlations," in Proc. DATE, 2006, pp. 528-532.