Benchmark tests for MOSFET compact models with application to the PSP model

IEEE Transactions on Electron Devices

Volumn 56, Issue 2, 2009, Pages 243-251

  Li, Xin ^a   Wu, Weimin ^a   Jha, Amit ^b   Gildenblat, Gennady ^a   van Langevelde, Ronald ^c   Smit, Geert D J ^d   Scholten, Andries J ^d   Klaassen, Dirk B M ^d   McAndrew, Colin C ^e   Watts, Josef ^f   Olsen, C Michael ^f   Coram, Geoffrey J ^g   Chaudhry, Samir ^h   Victory, James ⁱ  

^a ARIZONA STATE UNIVERSITY   (United States)

^b MAXIM INTEGRATED PRODUCTS   (United States)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d NXP Research   (Netherlands)

^e FREESCALE SEMICONDUCTOR INC   (United States)

^f IBM RESEARCH   (United States)

^g ANALOG DEVICES INC   (United States)

^h Jazz Semiconductor   (United States)

ⁱ Sentinel IC Technologies   (United States)

Author keywords

Benchmark tests; Compact model; MOSFET; Surface potential based model

Indexed keywords

LUMINOUS PAINT; MOSFET DEVICES; TESTING;

ANALOG APPLICATIONS; BENCHMARK TESTS; CMOS IC; COMPACT MODEL; EXPERIMENTAL DATUM; FUTURE GENERATIONS; LOW-POWER; MIXED SIGNALS; MOSFET; MOSFET COMPACT MODELS; PHYSICAL BEHAVIORS; SURFACE-POTENTIAL-BASED MODEL;

BENCHMARKING;

EID: 59849089851     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2010570     Document Type: Article

References (18)

1. G. Gildenblat, X. Li, W. Wu, H. Wang, A. Jha, R. van Langevelde, G. D. J. Smit, A. J. Scholten, and D. B. M. Klaassen, "PSP: An advanced surface-potential-based MOSFET model for circuit simulation," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 1979-1993, Sep. 2006.
2. W. Liu, MOSFET Models for Spice Simulation. New York: Wiley-Interscience, 2001.
3. C. McAndrew, "Practical modeling for circuit simulation," IEEE J. Solid State Circuits, vol. 33, no. 3, pp. 439-448, Mar. 1998.
4. C. McAndrew, H. Gummel, K. Singhal, and K. Singhal, "A comparison and evaluation of state-of-the-art compact MOSFET models," AT&T Bell Lab., Murray Hill, NJ, AT&T Bell Laboratories Technical Memorandum 52864-910119-01TM, 1991.
5. Y. Tsividis and K. Suyama, "MOSFET modeling for analog circuit CAD: Problems and prospects," IEEE J. Solid State Circuits, vol. 29, no. 3, pp. 210-216, Mar. 1994.
6. C. McAndrew, H. Gummel, and K. Singhal, "Benchmarks for compact MOSFET models," in Proc. SEMATECH Compact Models Workshop, Mar. 1995.
7. X. Li, W. Wu, A. Jha, G. Gildenblat, R. van Langevelde, G. D. J. Smit, A. J. Scholten, D. B. M. Klaassen, C. C. McAndrew, J. Watts, M. Olsen, G. Coram, S. Chaudhry, and J. Victory, "Benchmarking the PSP compact model for MOS transistors," in Proc. IEEE ICMTS, Mar. 2007, pp. 259-264.
8. H. C. Pao and C. T. Sah, "Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors," Solid State Electron., vol. 9, no. 10, pp. 927-937, Oct. 1966.
9. J. R. Brews, "A charge-sheet model of the MOSFET," Solid State Electron, vol. 21, no. 2, pp. 345-355, Feb. 1978.
10. P. Bendix, P. Rakers, P. Wagh, L. Lemaitre, W. Grabinski, C. McAndrew, X. Gu, and G. Gildenblat, "RF distortion analysis with compact MOSFET models," in Proc. IEEE CICC, Oct. 3-6 2004, pp. 9-12.
11. C. C. McAndrew, "Useful numerical techniques for compact modeling," in Proc. Int. Conf. Microelectron. Test Struct., Apr. 8-11, 2002, pp. 121-126.
12. K. Joardar, K. Gullapalli, C. McAndrew, M. Burnham, and A. Wild, "An improved MOSFET model for circuit simulation," IEEE Trans. Electron Devices, vol. 45, no. 1, pp. 134-148, Jan. 1998.
13. C. McAndrew, "Validation of MOSFET model source drain symmetry," IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2202-2206, Sep. 2006.
14. W. Wu, X. Li, G. Gildenblat, G. O. Workman, S. Veeraraghavan, C. McAndrew, R. van Langevelde, G. D. J. Smit, A. J. Scholten, and D. B. M. Klaassen, "A compact model for valence-band electron tunneling current in partially depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 54, no. 2, pp. 316-322, Feb. 2007.
15. T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998.
16. W. Wu, X. Li, G. Gildenblat, G. Workman, S. Veeraraghavan, C. C. McAndrew, R. van Langevelde, G. D. J. Smit, A. J. Scholten, D. B. M. Klaassen, and J. Watts, "PSP-SOI: A surface potential based compact model of partially depleted SOI MOSFETs," in Proc. IEEE CICC, Sep. 2007, pp. 41-48.
17. R. van Langevelde, A. J. Scholten, and D. B. M. Klaassen, Physical Background of MOS Model 11, 2003. [Online]. Available: http:// www.nxp.com/acrobat_download/other/philipsmodels/nl_tn2003_00239.pdf
18. N. Scheinberg and A. Pinkhasov, "A computer simulation model for simulating distortion in FET resistors," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 9, pp. 981-989, Sep. 2000.