Useful numerical techniques for compact modeling

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2002, Pages 121-126

  McAndrew, Colin C ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CONDUCTANCE; GATES (TRANSISTOR); NUMERICAL METHODS; RESISTORS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

BACKGATE BIAS; OUTPUT CONDUCTANCE;

MOSFET DEVICES;

EID: 0037819294     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. B. Ankele, W. Holzl, and P. O'Leary, "Enhanced MOS Parameter Extraction and SPICE Modeling for Mixed Analogue/Digital Circuit Simulation," Proc. ICMTS, pp. 73-78, 1989.
2. ∞-Continuous MOSFET Model Including Subthreshold Conduction," IEEE Electron Device Letters, vol. 12, no. 10, pp. 565-567, Oct. 1991.
3. Y. P. Tsividis, Operation and Modeling of the MOS Transistor, 2nd Edition, McGraw-Hill, 1999.
4. C. Lallement, M. Bucher, and C. Enz, "Modeling and Characterization of Non-Uniform Substrate Doping," Solid-State Electronics, vol. 41, no. 12, pp. 1857-1861, Dec. 1997.