Architecture and implementation of a low-power LVDS output buffer for high-speed applications

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 10, 2006, Pages 2101-2108

  Bratov, Vladimir ^a   Binkley, Jeb ^a,b   Katzman, Vladimir ^a   Choma, John ^b  

^a Advanced Science and Novel Technology   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Integrated circuits (ICs); Low voltage differential signaling; LVDS; Output buffer; Output driver; SiGe technology

Indexed keywords

COMPUTER SIMULATION; DEMULTIPLEXING; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE; MULTIPLEXING; SEMICONDUCTING SELENIUM COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES;

HIGH-SPEED INTEGRATED CIRCUITS; LOW-VOLTAGE DIFFERENTIAL SIGNALING (LVDS); OUTPUT BUFFER; OUTPUT DRIVER; POWER CONSERVING CIRCUIT;

INTEGRATED CIRCUITS;

EID: 33750427492     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.883164     Document Type: Article

References (13)

1. Electrical characteristics of low voltage differential signaling (LVDS) interface circuits, Standard ANSI/TIA/EIA-644 1995, Telecommunications Industry Association, Arlington, VA, Mar. 1996.
2. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI), IEEE Standard 1596.3-1996, Jul. 1996.
3. Space engineering: SpaceWire - links, nodes, routers and networks ECSS Secretariat, ESA-ESTEC Requirements & Standards Division, Noordwijk, The Netherlands, 2003, ECSS-E-50-12A.
4. M. Chen, J. Silva-Martinez, M. Nix, and M. E. Robinson, "Low-voltage low-power LVDS drivers," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 472-479, Feb. 2005.
5. G. Mandal and P. Mandal, "Low power LVDS transmitter with low common mode variation for 1 Gb/s-per pin operation," in Proc. IEEE Int. Symp. Circuits and Systems, Vancouver, Canada, May 2004, pp. 1120-1123.
6. A. Boni, A. Pierazzi, and D. Vecchi, "LVDS I/O interface for Gb/ s-per-pin operation in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
7. S. Jamasb, R. Jalilizinali, and P. M. Chau, "A 622 MHz stand-alone LVDS driver pad in 0.18-μm, CMOS," in Proc. 44th IEEE Int. Midwest Symp. Circuits and Systems, Dayton, OH, Aug. 2001, pp. 610-613.
8. T. Gabara, W. Fischer, W. Wemer, S. Siegel, M. Kothandaraman, P. Metz, and D. Gradl, in Proc. 10th IEEE Int. ASIC Conf., Portland, OR, Sep. 1997, pp. 311-315.
9. B. Young, "An SOI CMOS LVDS driver and receiver pair," in Dig. Tech. Papers 2001 Symp. VLSI Circuits, Jun. 2001, pp. 153-154.
10. A. Rivera, E. Bravo, M. Jimenez, and R. Palomera, "Design review and innovations in low-voltage differential signaling drivers," in Proc. 47th IEEE Int. Midwest Symp. Circuits and Systems, Japan, Jul. 2004, pp. 339-342.
11. K. Kishine et al., "A high-speed, low-power bipolar digital circuit for Gb/s LSIs: Current mirror control logic," IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 215-221, Feb. 1997.
12. K. Koike et al., "High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing," IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1536-1544, Oct. 1998.
13. G. Schuppener, C. Pala, and M. Mokhatri, "Investigation on low-voltage low-power silicon bipolar topology for high-speed digital circuits," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1051-1054, Jul. 2000.