Low power LVDS transmitter with low common mode variation for 1 GB/s-per pin operation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Mandal, Gunjan ^a   Mandal, Pradip ^a  

^a Alliance Semiconductor   (India)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; DIGITAL SIGNAL PROCESSING; ELECTRIC CONDUCTANCE; ELECTRIC POTENTIAL; ENERGY DISSIPATION; INTERFACES (MATERIALS); LIQUID CRYSTAL DISPLAYS; TRANSMITTERS;

COMMUNICATION RELIABILITY; FEEDBACK CIRCUIT; LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS); PIN DATA RATE;

CMOS INTEGRATED CIRCUITS;

EID: 4344601199     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. "The National Technology Roadmap for Semiconductors, "Semiconductor Industry Associations, 1997.
2. IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface(SCI), 1596.3 SCI-LVDS Standard, IEEE Std. 1596.3-1996, March 1996.
3. Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits. TIA/EIA-644. March 1996.
4. Andrea Boni,Andrea Pierazzi, Davide Vecchi,"LVDS I/O Interface for Gb/s-per-Pin Operation in .35um CMOS,"IEEE J. Solid-state circuits, vol.36, No.4, pp.706-711.April 2001.
5. SN75LVDS83, Flatlink Transmitter datasheet, SLLS27ID-March-1997-Revised MAy 2001, Texas Instruments Inc.
6. T. Gabara et al.,"LVDS I/O buffer with a controlled reference circuit," in proc. ASIC Conf., Sept. 1997, pp311-3
7. DS90LV047A 3V Quad CMOS Differential Line Driver data sheet, National Semiconductor Corp., January 2003.