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Volumn 2005, Issue , 2005, Pages 805-811

Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC LANGUAGES; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS;

EID: 33751435853     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560174     Document Type: Conference Paper
Times cited : (53)

References (11)
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    • M. Orshansky; L. Milor and C. Hu, "Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction," IEEE Trans. Semiconductor Manufacturing, vol. 17, no. 1, pp. 2-11, Feb. 2004.
    • (2004) IEEE Trans. Semiconductor Manufacturing , vol.17 , Issue.1 , pp. 2-11
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  • 4
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    • Model order-reduction of RC(L) interconnect including variational analysis
    • Y, Liu, L. Pileggi and A. Strojwas, "Model order-reduction of RC(L) interconnect including variational analysis," IEEE/ACMDAC, pp. 201-206, 1999.
    • (1999) IEEE/ACMDAC , pp. 201-206
    • Liu, Y.1    Pileggi, L.2    Strojwas, A.3
  • 5
    • 0035215357 scopus 로고    scopus 로고
    • Model reduction of variablegeometry interconnects using variational spectrally-weighted balanced truncation
    • P. Heydari and M. Pedram, "Model reduction of variablegeometry interconnects using variational spectrally-weighted balanced truncation," IEEE/ACM ICCAD, pp. 586-591, 2001.
    • (2001) IEEE/ACM ICCAD , pp. 586-591
    • Heydari, P.1    Pedram, M.2
  • 6
    • 16244379528 scopus 로고    scopus 로고
    • Stochastic analysis of interconnect performance in the presence of process variations
    • J. Wang, P. Ghanta and S. Vrudhula, "Stochastic analysis of interconnect performance in the presence of process variations," IEEE/ACM ICCAD, pp. 880-886, 2004.
    • (2004) IEEE/ACM ICCAD , pp. 880-886
    • Wang, J.1    Ghanta, P.2    Vrudhula, S.3
  • 7
    • 2542503566 scopus 로고    scopus 로고
    • A multi-parameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models
    • May
    • L. Daniel, O. Siong, L. Chay, K. Lee and J. White, "A multi-parameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models," IEEE Trans. CAD, vol. 23, no. 5, pp. 678-693, May. 2004.
    • (2004) IEEE Trans. CAD , vol.23 , Issue.5 , pp. 678-693
    • Daniel, L.1    Siong, O.2    Chay, L.3    Lee, K.4    White, J.5
  • 8
    • 0032139262 scopus 로고    scopus 로고
    • PRIMA: Passive reduced-order interconnect macromodeling algorithm
    • Aug.
    • A. Odabasioglu, M. Celik and L. Pileggi, "PRIMA: passive reduced-order interconnect macromodeling algorithm," IEEE Trans. CAD, vol. 17, no. 8, pp. 645-654, Aug. 1998.
    • (1998) IEEE Trans. CAD , vol.17 , Issue.8 , pp. 645-654
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  • 9
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    • Guaranteed passive balancing transforms for model order reduction
    • Aug.
    • J. Phillips, L. Daniel and L. Silveira, "Guaranteed passive balancing transforms for model order reduction," IEEE. Trans. CAD, vol. 22, no. 8, pp. 1027-1041, Aug. 2003.
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    • Phillips, J.1    Daniel, L.2    Silveira, L.3
  • 10
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    • E. Acar, F. Dartu and L. Pileggi, "TETA: transistor-level waveform evaluation for timing analysis," IEEE Trans. CAD, vol. 21, no. 5, pp. 605-616, May. 2002.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.