Probabilistic error modeling for nano-domain logic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 1, 2009, Pages 55-65

  Rejimon, Thara ^a   Lingasubramanian, Karthikeyan ^a   Bhanja, Sanjukta ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

Bayesian networks; Dynamic errors; Probabilistic error model

Indexed keywords

BAYESIAN NETWORKS; CIRCUIT SIMULATION; DESIGN; DISTRIBUTED PARAMETER NETWORKS; DYNAMIC MODELS; ERRORS; INFERENCE ENGINES; INTELLIGENT NETWORKS; INVERSE PROBLEMS; NETWORKS (CIRCUITS); PROBABILITY; SPEECH ANALYSIS; STOCHASTIC MODELS; SWITCHING CIRCUITS;

APPROXIMATE INFERENCES; BAYESIAN INFERENCES; BENCHMARK CIRCUITS; CIRCUIT DESIGNERS; COMPUTING ELEMENTS; DYNAMIC ERRORS; ERROR MODELING; ERROR PROBABILITIES; ERROR SENSITIVITIES; ERROR-TOLERANT; EXACT INFERENCES; HIGHLY SENSITIVES; INPUT SPACES; LOGIC MODELS; LOGIC SIMULATIONS; MEDIUM SIZES; MINIMAL REPRESENTATIONS; NP-HARD; OUTPUT CHARACTERISTICS; OUTPUT ERRORS; PROBABILISTIC ERROR MODEL; PROBABILISTIC FRAMEWORKS; PROBABILISTIC MODELS; STATE-OF-THE ARTS; STOCHASTIC SAMPLINGS; WORST CASE;

LOGIC CIRCUITS;

EID: 58849147595     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2003167     Document Type: Article

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